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Natalius_SoC
public project
MPW-6   

Natalius is a 8 bit RISC Processor, it was developed in the computer architecture course with the support of students from the Universidad Pontificia Bolivariana in Medellin. The project was initially implemented in FPGA and now it is migrated to be implemented on a 130nm process ASIC.

Natalius contains the typical instruction set on a processor. These are: Memory access, arithmetic, logical and flow control.

Features:

1. 8 Bit ALU
2. 8x8 Register File
3. 2048x16 Instruction Memory
4. 32x8 Ram Memory
5. 16x11 Stack Memory
6. Three CLK / Instruction
7. Carry and Zero flags
8. 8 bit Address Port (until 256 Peripherals)

 

 


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Description

Natalius is a compact, capable and fully embedded 8 bit RISC processor core described 100% in Verilog. This processor includes a very tiny VGA Controller suitable for VideoGames :)

Category

processor

Process

sky130A