Caravan

Overview

Caravan is a design template for creating your own semi-custom ASIC as part of Efabless chipIgnite solution with the open-source SKY130 PDK for the 130nm CMOS Skywater technology process. caravan includes a 10 mm2 user area on the chip for implementing your custom design.

The carrier chip provides all the infrastructure required for building a chip including IO and power, clock, reset, and a management SoC that can be used to drive your project. The management SoC includes a RISC-V processor, memory and a wishbone bus that extends into the user area for connecting your own peripherals.

Caravan is very similar to caravan, the only difference is that Caravan has 11 bare pads, which supports high speed and -ve voltages, but lacks the ESD protection. Caravan is only suitable for prototyping, not production. We highly recommend using caravan if you are not an expert in Analog designs

design+caravan

License

Caravan is an open-source design licensed under the terms of Apache 2.0. The design can be found at GitHub in the efabless/caravel repository.

Features:

27 programmable IO
11 high speed IO
10 mm2 of user project area
VexRiscv core with serial and SPI debug ports
1.5 kbytes of RAM
SPI Flash controller supporting XIP
UART, SPI and GPIO ports
128 port logic analyzer
Counter / timer
32-bit wishbone bus extending to the user
project area
6 user interrupts
DLL, PoR
33 MHz
User power domains:
- 2 digital domains, 1.71 to 1.89 V
- 2 analog domain, 3.0 to 5.5 V
Other power domains:
- vccd, SoC core voltage, 1.8V nom
- vddio / vdda, IO output driver voltage, 3.3 to 5.0V nom
Packages available
- QFN 64L
- WCSP 60 ball
- Bare die
Temperature range, 0 to 70 deg C