Caravel Mini

Overview

Caravel Mini is a project template provided by Efabless, allowing up to four projects to be integrated into a single chip. This template is ideal for prototyping small designs that do not require the entire user_project_wrapper, making it a cost-effective solution that still offers substantial benefits.

The Caravel Mini template divides the user project area into four distinct sections within the Caravel chip's user project space, as illustrated in the image below:

Switching between projects is facilitated by a multiplexer (mux) that selects projects based on IOs 36 and 37. For this project, you only need to focus on your user project design. Efabless will handle the integration of your design into the Caravel Mini template and subsequently into Caravel through our Tapeout process.

This template can be shared with other users, and you have the option to keep your project private if desired. Other teams sharing the same chip will not have access to your project's documentation, GDS, or any other files.

Features:

• Area of each project is 1300 um x 1600 um
• 36 programmable GPIOs
• 32 Logic Analyzer probes
• 32 bit Wishbone bus connected to the mgmt SoC
• 1 digital power domain

Caravel support features:

• VexRiscv core with serial and SPI debug ports
• 1.5 kbytes of RAM
• SPI Flash controller supporting XIP
• UART, SPI and GPIO ports
• Counter / timer
• DLL, PoR
• 33 MHz

Start Caravel Mini project

To start the Caravel Mini project, please visit the Caravel Mini user project example Github Repo, and for more infromation about Caravel Mini visit the knowledge base blog on Caravel Mini.