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Caravel Analog Project

Caravel Analog Project

Caravel Analog Project

Overview

The Caravel Analog Project is a unique offering within the Caravel chip design framework that allows users to integrate their custom analog designs into a predefined space. This space, known as the user project area, is part of the overall Caravel chip and is specifically designated for user-defined logic. By utilizing the Caravel User Project, designers can incorporate their unique functionalities into a larger, professionally managed chip infrastructure, making it ideal for prototyping and small-scale production.

One of the key advantages of the Caravel Analog Project is its accessibility. It allows designers, regardless of their resources, to participate in silicon design and production. By providing a shared infrastructure and community support, Efabless lowers the barrier to entry, fostering innovation and collaboration in the field of chip design.

To ensure that all user designs are compliant with industry standards and compatible with the Caravel framework, Efabless has established a set of design rules. These rules are enforced through the precheck and tapeout flows, which are mandatory steps in the design process. The precheck flow validates the design against the specified rules, while the tapeout flow prepares the design for fabrication.

By integrating their custom designs into the Caravel User Project, users benefit from the robust features of the Caravel chip, including a RISC-V core, multiple I/O interfaces, and comprehensive debugging capabilities. This integration enables rapid development and testing of new ideas, significantly reducing time-to-market and development costs.

Analog designs can be integrated in either Caravel or Caravan, the only difference is that Caravan has bare pads, for experienced designers. Caravan should only be used if you are experienced, and the design is meant to be used in a controlled enviroment in a lab, it is only meant for prototyping. Otherwise, users designing analog projects are recommended to use Caravel.

Flow

Features:

  • Area of user project is 2.92 mm x 3.52 mm
  • 38 programmable GPIOs
  • 128 Logic Analyzer probes
  • 32 bit Wishbone bus connected to the mgmt SoC
  • 2 digital power domains
  • 2 analog power domains

floorplan

Caravel support features:

  • VexRiscv core with serial and SPI debug ports
  • 1.5 kbytes of RAM
  • SPI Flash controller supporting XIP
  • UART, SPI and GPIO ports
  • Counter / timer
  • DLL, PoR
  • 33 MHz

Getting Started

To start developing with the Caravel User Project, visit the Caravel User Project Example GitHub Repository. The repository contains detailed documentation, examples, and resources to help you integrate your custom design into the Caravel framework.

By leveraging the Caravel User Project, designers can rapidly prototype and tape out custom logic in a streamlined and cost-effective manner, taking advantage of the robust infrastructure provided by Efabless.

Summary

Catalog ID

CARAVEL ANALOG PROJECT

Vendor

Efabless

Category

Silicon Services

Price & Licensing

Pricing

Free

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