The user project is a simple Power on Reset (PoR) that showcases how to make use of caravel's user space utilities like IO pads, logic analyzer probes, and wishbone port. The repo also demonstrates the recommended structure for the efabless' shuttle projects.
The power-on-reset circuit is simple and is not compensated for temperature or voltage variation. When the power supply reaches a sufficient level, the voltage divider sets the gate voltage on an nFET device to draw a current of nominally 240nA. A cascaded current mirror divides down the current by a factor of ~400. The output ~600pA from the end of the current mirror is accumulated on a capacitor until the value trips the input of the 3.3v Schmitt trigger buffer from the sky130_fd_sd_hvl library. The capacitor is sized to peg the nominal time to trigger at 15ms.
The output of the Schmitt trigger buffer becomes the high-voltage output, and is input to a standard buffer and inverter used as level shifters from the 3.3V domain to the 1.8V domain, producing complementary low-voltage outputs.
The user project is formed from two power-on-reset circuits, one of which is connected to the user area VDDA1 power supply, and the other of which is connected to one of the analog I/O pads, used as a power supply input and connected to its voltage ESD clamp circuit. The 3.3V domain outputs are connected directly to GPIO pads through the ESD 150 ohm series connection. The 1.8V domain outputs are connected to GPIO pads through the usual I/O connections, with the corresponding user output enable (sense inverted) held low to keep the output always active.
For more information and setup/implementation documentation visit Caravel Analog User Project Example Github Repo
ANALOG USER PROJECT
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