A Universal Asynchronous Receiver/Transmitter (UART) Soft IP with the following features:
EF_UART
comes with APB, AHB and WB bus wrappers in Verilog HDL; based on your use case, use one of these wrappers or create your own wrapper for your system bus type.
The EF_UART
tx
and rx
ports must be connected, both or one of them, to an input I/O pad for rx
and an output I/O pad for tx
.
The I/O registers are provided by the bus wrapper. This section applies to all provided bus wrappers.
Name | Offset | Reset Value | Access Mode | Description |
---|---|---|---|---|
RXDATA | 0000 | 0x00000000 | r | RX Data register; the interface to the Receive FIFO. |
TXDATA | 0004 | 0x00000000 | w | TX Data register; ; the interface to the Receive FIFO. |
PR | 000c | 0x00000000 | w | The Prescaler register; used to determine the baud rate. Baud_rate = Bus_Clock_Freq/((Prescaler+1)*16) |
CTRL | 0008 | 0x00000000 | w | UART Control Register |
CFG | 0010 | 0x00003F08 | w | UART Configuration Register |
FIFOCTRL | 0014 | 0x00000000 | w | FIFO Control Register |
FIFOS | 0018 | 0x00000000 | r | FIFO Status Register |
MATCH | 001c | 0x00000000 | w | Match Register |
IM | 0f00 | 0x00000000 | w | Interrupt Mask Register; write 1/0 to enable/disable interrupts; check the interrupt flags table for more details |
RIS | 0f08 | 0x00000000 | w | Raw Interrupt Status; reflects the current interrupts status;check the interrupt flags table for more details |
MIS | 0f04 | 0x00000000 | w | Masked Interrupt Status; On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect; check the interrupt flags table for more details |
IC | 0f0c | 0x00000000 | w | Interrupt Clear Register; On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared; check the interrupt flags table for more details |
RX Data register; the interface to the Receive FIFO.
TX Data register; ; the interface to the Receive FIFO.
The Prescaler register; used to determine the baud rate. Baud_rate = Bus_Clock_Freq/((Prescaler+1)*16)
UART Control Register
bit | field name | width | description |
---|---|---|---|
0 | en | 1 | UART enable |
1 | txen | 1 | UART Transmitter enable |
2 | rxen | 1 | UART Receiver enable |
3 | lpen | 1 | Loopback (connect RX and TX pins together) enable |
4 | gfen | 1 | UART Glitch Filer on RX enable |
UART Configuration Register
bit | field name | width | description |
---|---|---|---|
0 | wlen | 4 | Data word length: 5-9 bits |
4 | stp2 | 1 | Two Stop Bits Select |
5 | parity | 3 | Parity Type: 000: None, 001: odd, 010: even, 100: Sticky 0, 101: Sticky 1 |
8 | timeout | 6 | Receiver Timeout measured in number of bits |
FIFO Control Register
bit | field name | width | description |
---|---|---|---|
0 | TXLT | 4 | Transmit FIFO Level Threshold |
8 | RXLT | 4 | Receive FIFO Level Threshold |
FIFO Status Register
bit | field name | width | description |
---|---|---|---|
0 | RXL | 4 | Receive FIFO Level |
8 | TXL | 4 | Transmit FIFO Level |
Match Register
The following are the bit definitions for the interrupt registers: IM, RIS, MIS, and IC.
Bit | Flag | Width | Description |
---|---|---|---|
0 | TXE | 1 | Transmit FIFO is Empty. |
1 | RXF | 1 | Receive FIFO is Full. |
2 | TXB | 1 | Transmit FIFO level is Below Threshold. |
3 | RXA | 1 | Receive FIFO level is Above Threshold. |
4 | BRK | 1 | Line Break; 13 consecutive 0's have been detected on the line. |
5 | MATCH | 1 | Match; the receive data matches the MATCH register. |
6 | FE | 1 | Framing Error; the receiver does not see a "stop" bit at the expected "stop" bit time. |
7 | PRE | 1 | Parity Error; the receiver calculated parity does not match the received one. |
8 | OR | 1 | Overrun; data has been received but the RX FIFO is full. |
9 | RTO | 1 | Receiver Timeout; no data has been received for the time of a specified number of bits. |
Parameter | Description | Default Value |
---|---|---|
SC | Number of samples per bit/baud | 8 |
MDW | Max data size/width | 9 |
GFLEN | Length (number of stages) of the glitch filter | 8 |
FAW | FIFO Address width; Depth=2^AW | 4 |
Port | Width | Direction |
---|---|---|
prescaler | 16 | input |
en | 1 | input |
tx_en | 1 | input |
rx_en | 1 | input |
wdata | MDW | input |
timeout_bits | 6 | input |
loopback_en | 1 | input |
glitch_filter_en | 1 | input |
tx_level | FAW | output |
rx_level | FAW | output |
rd | 1 | input |
wr | 1 | input |
data_size | 4 | input |
stop_bits_count | 1 | input |
parity_type | 3 | input |
txfifotr | FAW | input |
rxfifotr | FAW | input |
match_data | MDW | input |
tx_empty | 1 | output |
tx_full | 1 | output |
tx_level_below | 1 | output |
rdata | MDW | output |
rx_empty | 1 | output |
rx_full | 1 | output |
rx_level_above | 1 | output |
break_flag | 1 | output |
match_flag | 1 | output |
frame_error_flag | 1 | output |
parity_error_flag | 1 | output |
overrun_flag | 1 | output |
timeout_flag | 1 | output |
rx | 1 | input |
tx | 1 | output |
PR
registerwlen
field in the CFG
registerstb2
bit in CFG
register where ‘0’ means one bit and ‘1’ means two bitsparity
field in CFG
register where 000: None, 001: odd, 010: even, 100: Sticky 0, 101: Sticky 1RTO
interrupt after a certain amount of bits are received. This would be useful when the message received is not a multiple of the FIFO’s width. Timeout can be set by writing to the timeout
field in the CFG
registerRXLT
and TXLT
fields in FIFOCTRL
register. This would fire RXA
and TXB
interrupts when the RX FIFO level is above the threshold and TX FIFO level is below the threshold.en
, txen
, and rxen
bits to ones in the CTRL
registerloopback
bit to one in the CTRL
register.gfen
bit to one in the CTRL
register.RXDATA
register. Note: you should check that there is something in the FIFO before reading using the interrupts registers.MATCH
register. This would fire the MATCH
interrupt if the received data matches the match value.TXDATA
register. Note: you should check that the FIFO is not full before adding something to it using the interrupts register to avoid losing data.You can either clone repo or use IPM which is an open-source IPs Package Manager
To clone repo git clone https://github.com/efabless/EF_UART.git
To download via IPM , follow installation guides here then run ipm install EF_UART
Clone IP_Utilities repo under EF_UART/
directory
In the directory EF_UART/verify/utb/
run make APB-RTL
TBD
EF_UART
Vendor
Efabless
UART
Free
Open Source
Apache
EF Certified
Integrated