EF_GPIO8

A generic 8-bit General Purpose I/O (GPIO) Peripheral with the following features

• Eight bidirectional pins.
• Input synchronizers
• Input edge detectors.
• Direction control.
• Edge and Level Interrupts generation per pin.
• Wrappers for AHB-Lite, APB and WB buses.

General Information

• Maturity: Integrated
• Certification: EF Certified
• Provider: Efabless
• License: Apache Open Source
• Category: General Purpose I/O
• Foundry: Skywater
• Node: 130nm
• PDK: SKY130

The Wrapped IP

APB and AHBL wrappers, generated by the IP_Utilities amba_wrap.py utility, is provided. WB wrapper will be provided soon. All wrappers provide the same programmer's interface as outlined in the following sections.

Wrapped IP System Integration

Based on your use case, use one of the provided wrappers or create a wrapper for your system bus type. For an example of how to integrate the APB wrapper:

EF_GPIO8_APB INST (
        `TB_APB_SLAVE_CONN,
        .io_in(io_in)
        .io_out(io_out)
        .io_oe(io_oe)
);

NOTE: `TB_APB_SLAVE_CONN is a convenient macro provided by IP_Utilities.

Implementation example

The following table is the result for implmenting the EF_GPIO8 IP with different wrappers using Sky130 PDK and yosys.

The Programming Interface

Registers

DATAI Register [Offset: 0x0, mode: r]

Data In Register; Reading from this register returns the pins status (8 pins); one bit per pin.

DATAO Register [Offset: 0x4, mode: w]

Data Out Register; Writing to this register change the status of the port pins (8 pins); one bit per pin.

DIR Register [Offset: 0x8, mode: w]

Direction Register; One bit per pin 1: output, 0: input.

Interrupt Flags

The wrapped IP provides four registers to deal with interrupts: IM, RIS, MIS and IC. These registers exist for all wrapper types generated by the IP_Utilities amba_wrap.py utility.

Each register has a group of bits for the interrupt sources/flags.

• IM: is used to enable/disable inetrrupt sources.
• RIS: has the current interrupt status (interruot flags) whether they are enabled or diabled.
• MIS: is the result of masking (ANDing) RIS by IM.
• IC: is used to clear an inetrrupt flag.

The following are the bit definitions for the interrupt registers:

The Interface

Ports

F/W Usage Guidelines:

1. Write to the direction register the direction of the GPIOs where '1' means gpio is output and '0' means gpio is input
2. To drive a gpio pin, write to the DATAO register
3. To read the value of a gpio pin , read from the DATAI register

Installation:

You can either clone repo or use IPM which is an open-source IPs Package Manager

• To clone repo: git clone https://github.com/efabless/EF_GPIO8
• To download via IPM , follow installation guides here then run ipm install EF_GPIO8

Simulation:

Run Verilog Testbench:

1. Clone IP_Utilities repo in the same directory as the IP
2. In the directory EF_GPIO8/verify/utb/ run make APB-RTL to run testbench for APB or make AHBL-RTL to run textbench for AHBL

Run cocotb UVM Testbench:

TBD