EF_TMR32

A 32-bit timer and PWM generator with the following features:

• 32-bit prescaler.
• Up Counting, Down Counting and Up/Down Counting.
• One-shot and Periodic.
• Two independent PWM channels with two compare registers.
• Optional PWM signal inversion.
• Configurable PWM dead time/band to generate PWM signals such as those required by a half-H bridge driver.
• Fault handeling.

General Information

• Maturity: Integrated. The circuit has been integrated into an IC and has either taped out, or will soon be taped out.
• Certification: EF Certified
• Provider: Efabless
• License: Apache Open Source
• Category: Timer
• Foundary: Skywater
• Node: 130nm
• PDK: SKY130

The Wrapped IP

APB and AHBL wrappers, generated by the IP_Utilities amba_wrap.py utility, is provided. WB wrapper will be provided soon. All wrappers provide the same programmer's interface as outlined in the following sections.

Wrapped IP System Integration

Based on your use case, use one of the provided wrappers or create a wrapper for your system bus type. For an example of how to integrate the APB wrapper:

EF_TMR32_APB INST (
        `TB_APB_SLAVE_CONN,
        .pwm0(pwm0)
        .pwm1(pwm1)
        .pwm_fault(pwm_fault)
);

NOTE: `TB_APB_SLAVE_CONN is a convenient macro provided by IP_Utilities.

Implementation example

The following table is the result for implmenting the EF_TMR32 IP with different wrappers using Sky130 PDK and yosys.

The Programming Interface

Registers

TMR Register [Offset: 0x0, mode: r]

The current value of the Timer.

RELOAD Register [Offset: 0x4, mode: w]

The timer reload value. In up counting it is used as the terminal count. For down counting it is used as the initial count.

PR Register [Offset: 0x8, mode: w]

The Prescaler. The timer counting frequency is Clock\ freq/(PR + 1)

CMPX Register [Offset: 0xc, mode: w]

Compare Register X

CMPY Register [Offset: 0x10, mode: w]

Compare Register Y.

CTRL Register [Offset: 0x14, mode: w]

Control Register.

CFG Register [Offset: 0x18, mode: w]

Configuration Register.

PWM0CFG Register [Offset: 0x1c, mode: w]

PWM0 Configuration Register.

PWM1CFG Register [Offset: 0x20, mode: w]

PWM1 Configuration Register.

PWMDT Register [Offset: 0x24, mode: w]

PWM deadtime Register.

Interrupt Flags

The wrapped IP provides four registers to deal with interrupts: IM, RIS, MIS and IC. These registers exist for all wrapper types generated by the IP_Utilities amba_wrap.py utility.

Each register has a group of bits for the interrupt sources/flags.

• IM: is used to enable/disable inetrrupt sources.
• RIS: has the current interrupt status (interruot flags) whether they are enabled or diabled.
• MIS: is the result of masking (ANDing) RIS by IM.
• IC: is used to clear an inetrrupt flag.

The following are the bit definitions for the interrupt registers:

The Interface

Module Parameters

Ports

F/W Usage Guidelines:

• To use the timer only:

1. Set the value of reload (the maximum value the timer counter will reach if up counting or the value it will start from when down counting) by writing to RELOAD register.
2. Set the timer counting frequency by writing to the PR register where the timer counting frequency is Clock\ freq/(PR + 1).
3. Choose whether you want the timer counter to be up counting, down counting, up/down counting by setting the DIR field in CFG register.
4. Choose whether you want the timer counter to be periodic (starts counting again after reaching reload value) or one shot (count only one time and stays at reload value) by setting the P field in CFG register.
5. Enable the timer by setting TE field in CTRL register , if one shot mode is used, use TS field to restart the counter.
6. Get the actual timer value through reading TMR register.

• To generate PWM signals:

1. Do the exact same steps (from 1 to 5) for using the timer.
2. Set the values for the two compare registers, if needed, by writing to CMPX and CMPY registers.
3. Choose the actions you want when the timer reaches each of zero, cmpx (up counting), cmpy (up counting), reload, cmpx (down counting), cmpy (down counting). The actions could be either no action, high, low, or invert. You can set the actions by writing to PWM0CFG if using pwm0 or PWM1CFG if using pwm1.
4. Enable the timer, and enable pwm0 and/or pwm1 by writting to CTRL register.

Installation:

You can either clone repo or use IPM which is an open-source IPs Package Manager

• To clone repo: git clone https://github.com/efabless/EF_TMR32/tree/main
• To download via IPM , follow installation guides here then run ipm install EF_TMR32

Simulation:

Run Verilog Testbench:

1. Clone IP_Utilities repo in the same directory as the IP.
2. In the directory EF_TMR32/verify/utb/ run make APB-RTL to run testbench for APB or make AHBL-RTL to run textbench for AHBL.

Run cocotb UVM Testbench:

TBD