EF_QSPI_XIP_CACHE

General Information

• Maturity: Integrated. The circuit has been integrated into an IC and has either taped out, or will soon be taped out.
• Certification: EF Certified
• Provider: Efabless
• License: Open Source
• Catagory: SPI
• Foundary: Skywater
• Node: 130nm
• PDK: SKY130

Overview

Quad I/O SPI Flash memory controller with support for:

• AHB lite interface
• Execute in Place (XiP)
• Nx16 Direct-Mapped Cache (default: N=32).

This block is intended to be used with SoCs that have no on-chip flash memory.

Todo:

• Support for WB bus.
• Support cache configurations other than 16 bytes per line.

Performance

The following data is from the SKY130 HD library:

| Configuration | # of Cells (K) | Delay (ns) | Idyn (mA/MHz) | Is (nA) | | :---: | :---: | :---: | :---: | | 16x16 | 7.2 | 12 | 0.0625 | 20 | | 32x16 | 14.3 | 17 | 0.126 | 39.5 |

Installation 

• To clone repo git clone https://github.com/efabless/EF_QSPI_XIP_CACHE.git

• To download via IPM ipm install EF_QSPI_XIP_CACHE

Running Simulation

Run the following in the directory verify/utb

For RTL simulation: make SIM-RTL

For GL simulation: make SIM-GL