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EF_QSPI_XIP_CACHE

Efabless

EF_QSPI_XIP_CACHE

Quad I/O SPI Flash memory controller with support for:

  • AHB lite interface
  • Execute in Place (XiP)
  • Nx16 Direct-Mapped Cache (default: N=32).

This block is intended to be used with SoCs that have no on-chip flash memory.

Todo:

  • Support for WB bus.
  • Support cache configurations other than 16 bytes per line.

Performance

The following data is from the SKY130 HD library:

| Configuration | # of Cells (K) | Delay (ns) | Idyn (mA/MHz) | Is (nA) | | :---: | :---: | :---: | :---: | | 16x16 | 7.2 | 12 | 0.0625 | 20 | | 32x16 | 14.3 | 17 | 0.126 | 39.5 |

Installation

  • To clone repo git clone https://github.com/efabless/MS_QSPI_XIP_CACHE.git

  • To download via IPM ipm install MS_QSPI_XIP_CACHE

Running Simulation

Run the following in the directory verify/utb

For RTL simulation: make SIM-RTL

For GL simulation: make SIM-GL

Summary

Catalog ID

EF_QSPI_XIP_CACHE

Provider

Vendor

Vendor

Efabless

Node

130nm

Foundry

Skywater

Category

SPI

Licensing

Info

Open Source (Free)

Quality

Certification

EF Certified

Maturity

Implemented