NOTE: To inquire about using this commercial IP in your project, please get in touch with Efabless: shuttle@efabless.com
This is a 1024 words by 32 bits (4kByte) commercial grade low power embedded Single Port Synchronous (flow through) SRAM in SKY130 technology, in a compact 0.165 mm² area.
An active high read-write enable signal controls the read/write operation of the memory. When bit-enable is high and readwrite enable is low, data on the data input pin is written into the memory location addressed by the address present on the address pins. Reading the device is accomplished while read-write enable is high. Under these conditions, the contents of the location addressed by the information on address lines is present on the data output pin. In write cycle, data to be written is driven onto data output pin. If there is no read or write, while memory is enabled, data output pin will hold previous data.
Memory dimensions in SKY130 technology: 380 um x 435 um = 0.165 mm²
A wishbone interface wrapper version is also available.
You can either clone repo or use IPM which is an open-source IPs Package Manager
git clone https://github.com/efabless/EF_SRAM_1024X32ipm install EF_SRAM_1024X32For instructions on integrating this IP into your project, see the following article.
| NAME | TYPE | DIRECTION | DESCRIPTION |
|---|---|---|---|
| AD [9:0] | CMOS | IN | This input value selects the location to be read during a read cycle, and the location to be written during a write cycle. It is sampled on rising edge of clock. |
| R_WB | CMOS | IN | This is the read/write control and sampled on rising edge of clock. When R_WB is high, the memory is in a read cycle mode. When R_WB is low, the memory is in write cycle mode. |
| CLKin | CMOS | IN | Clock synchronizes the operations of the memory. All inputs are sampled on rising edge of clock. |
| BEN [31:0] | CMOS | IN | Each bit of the BEN bus selects one bit of the DI bus. When one or more BEN inputs are high (active), and R_WB is low (write enabled) then the selected bits will be written into the memory. |
| DI [31:0] | CMOS | IN | This data is written into the memory location selected by addr inputduring the write cycle. It is ignored during a read cycle. |
| EN | CMOS | IN | EN (Chip Enable) is high (and TM low), read and write operation is performed. |
| TM | CMOS | IN | When TM (Testmode)is high, memory is in testmode and normal memory operation is disabled. Inputs are tied to outputs through scan chain logic. |
| SM | CMOS | IN | When SM (Scan chain control) is high, output of a input register is passed to next register. When low, input register receives input from input pin. |
| WLBI | CMOS | IN | Wafer Level Burn-In Test mode control: When high, all wordlines are ON. |
| WLOFF | CMOS | IN | Normal operation when low. All wordlines are clamped to vnb when high. |
| ScanInCC | CMOS | IN | Input to Address and Control scan chain. ScanInDL |
| ScanInDL | CMOS | IN | Input to Data scan chain (left side of the macro). |
| ScanInDR | CMOS | IN | Input to Data scan chain (right side of the macro). |
| DO [31:0] | CMOS | OUT | Data from the memory location selected by address is driven onto DO during a read cycle. In a write cycle, data to be written is driven onto DO. If there is no read or write, while memory is enabled, DO will hold previous data. |
| ScanOutCC | CMOS | OUT | Output of Scan Chain of address and control pins. Note - DO is output of scan chain of data input pins. |
Without the Power Switch feature enabled (default recommended mode)
| NAME | TYPE | DIRECTION | DESCRIPTION |
|---|---|---|---|
| vpwrm | Supply | IN | Connect vpwrm to core power supply vpwra |
| vpwra | Supply | IN | Nominal 1.8 power supply to memory array |
| vpwrp | Supply | IN | Nominal 1.8 power supply to periphery |
| vpwrac | Supply | IN | Connect vpwrac to core power supply vpwra |
| vpwrpc | Supply | IN | Connect vpwrpc to core power supply vpwra |
| vgnd | Supply | IN | Nominal 0 V power supply (ground). |
| vpb | Bias Voltage | IN | Nwell connection, tie to the maximum power supply (can be vpwra or vpwrp) |
| vnb | Bias Voltage | IN | Pwell connection, nominally equal to vgnd |
With the Power Switch feature enabled
| NAME | TYPE | DIRECTION | DESCRIPTION |
|---|---|---|---|
| vpwrm | Supply | IN | Nominal 1.8 main power supply |
| vpwra | Supply | IN | power supply to memory array (internal node) |
| vpwrp | Supply | IN | power supply to periphery (internal node) |
| vpwrac | Supply | IN | Control signal to turn on the power supply to periphery (active LOW, CMOS) |
| vpwrpc | Supply | IN | Control signal to turn on the power supply to core (active LOW, CMOS) |
| vgnd | Supply | IN | Nominal 0 V power supply |
| vpb | Bias Voltage | IN | Nwell connection, tie to the maximum power supply (can be vpwrm) |
| vnb | Bias Voltage | IN | Pwell connection, nominally equal to vgnd |
Conditions
Power Dissipation When R_WB=HIGH
Power Dissipation When R_WB=LOW
Power Dissipation When EN=LOW, All Other Inputs Switching
Power Dissipation When TM=HIGH, Clock Switching
Leakage: Power switches ON, Disabled (EN=LOW)
**Leakage - One or More Power switches OFF (VPWRPC=HIGH or VPWRAC=HIGH)
Conditions
| DESCRIPTION | SYMBOL | MIN SPEC (ns) | MAX SPEC (ns) | ACTUAL (ns) |
|---|---|---|---|---|
| Cycle Time | Tcyc | 8.0 | ||
| Clock High Time | Tchi | 4.0 | ||
| Clock Low Time | Tclo | 4.0 | ||
| Clock to data-out (Read Cycle) | Trd | 0.5 | 4.74 | Rise: 2.4 Fall: 2.5 |
| Clock to data-out (Write Cycle) | Twr | 0.5 | 4.0 | Rise: 2.04 Fall: 2.1 |
| Setup time of addr/ctrl to clk | Tsad | 0.5 | Rise: 0.5 Fall: 0.6 | |
| Setup time of EN to clock | Tsen | 1.3 | 1.4 | |
| Hold time of addr/ctrl from clk | Thad | 0.7 | Rise: 0.3 Fall: 0.3 | |
| Setup time of Data to clk | Tsdi | 0.7 | 0.8 | |
| Hold time of data from clk | Thdi | 1.0 | 0.5 | |
| Setup time of BEN to clk | Tsben | 0.7 | 0.8 | |
| Hold time of BEN from clk | Thben | 1.0 | 0.5 |
Test Mode Parameters
| DESCRIPTION | SYMBOL | MIN SPEC (ns) | MAX SPEC (ns) | ACTUAL (ns) |
|---|---|---|---|---|
| Clock to data-out (Test Mode) | Tcotm | 0.15 | 3.6 | Rise: 1.6 Fall: 1.6 |
| Clock to ScanOutC (Test Mode) | Tcotm | 0.15 | 3.6 | Rise: 1.7 Fall: 1.7 |
| Setup time of Add & Control to clk (Test Mode) | Tsctl_tm | 0.8 | Rise: 0.85 Fall: 0.88 | |
| Hold time of Add & Control to clk (Test Mode) | Thctl_tm | 0.6 | Rise: 0.57 Fall: 0.57 | |
| Setup time of TM, SM to clk | Tstm | 6.5 | 6.5 | |
| Hold time of TM, SM from clk | Thtm | 1.0 | 1.0 |
EF_SRAM_1024X32
Vendor
Efabless
130nm
Skywater
Static Random-Access Memory
Paid
Vendor
Proprietary
EF Certified
Integrated