This IP is a bandgap referenced Power On Reset (POR). It was taped out on the CI2404 Chipalooza tapeout. The specifications below are target specifications. Check back for characterized numbers once the silicon is characterized.
| Pin name | Use | Domain | Notes |
|---|---|---|---|
| avdd | analog power | 3.3V | |
| dvdd | digital power | 1.8V | |
| avss | analog ground | ||
| dvss | digital ground | ||
| vbg | input bandgap reference | ||
| por | reset | dvdd domain | sense positive |
| porb | reset bar | dvdd domain | sense negative |
| porb_h | reset bar | avdd domain | sense negative |
| Parameter | Min | Typical | Max | Unit | Notes |
|---|---|---|---|---|---|
| Operating Temperature | -40 | 25 | 85 | °C | |
| Reset Threshold Voltage | 2.4 | 2.7 | 3 | V | V_th where reset is released |
| Hysteresis Voltage | 0.1 | 0.2 | 0.3 | V | Difference between reset assert and deassert levels |
| Reset Active Time | 30 | 50 | 100 | ms | Time after V_th for reset to deactivate |
| Reset Output Voltage (Low) | 0 | 0.1 | 0.3 | V | When in reset state |
| Reset Output Voltage (High) | 2.7 | 3.3 | 5.5 | V | When not in reset state |
| Power Consumption | 3 | 5 | µA | ||
| Output Leakage Current | 0 | 1 | 10 | nA | When reset is not active |
| Output Capacitive Load | 1 | 10 | 20 | pF | Distributed chip-wide |
| Start-Up Time | 0.5 | 1 | 2 | ms | Time from supply stable to POR active |
EF_POR
Vendor
Efabless
130nm
Skywater
Power Module
Open Source (Free)
EF Certified
Integrated