COMING SOON

Programmable PLL

This is a Programmable PLL designed in the Skywater 130nm Sky130A process.

Pin name	Use	Voltage Domain	Note
avdd	analog power	3.3-5.5V
dvdd	digital power	1.8V
avss	analog ground
dvss	digital ground
resetb	reset	dvdd domain	negative sense
ena	enable	dvdd domain	positive sense
ibias	bandgap-referenced current bias
fbdiv[5:0]	feedback divider (integer part)	dvdd domain
fbfrac[2:0]	feedback divider (fractional part)	dvdd domain
odiv1[3:0]	primary output divider	dvdd domain	core
odiv2[3:0]	secondary output divider	dvdd domain	peripheral
clkout1	primary clock output	dvdd domain
clkout2	secondary clock output	dvdd domain
clkref	reference clock input	dvdd domain

Parameter	Min	Typical	Max	Unit	Notes
Output Frequency Range	86	96	106	MHz
Supply Voltage	3	3.3	5.5	V
Input frequency range	4		16		Matches the HSXO specification
Operating Temperature	-40	25	85	°C
Power Consumption			50	uA	Measured at 3.3V and 25°C
Startup time			60	us
Lock Time			60	us	Measured at input frequency 10 MHz
Jitter (RMS)	-300		300	ps	Meets USB 1.2 full speed specification
Cycle-cycle jitter			93	ps	Meets USB 1.2 full speed specification
Output Duty Cycle	45	50	55	%
Frequency Accuracy	-0.25	0	0.25	%	At 25°C
Output Rise/Fall Time	0.5	1	2	ns	10-90% of V_max
Output Load Capacitance			100	fF	Output will be buffered
Feedback divider value	1		31.875		In steps of 0.125
Output divider value	1		8		Integer