This IP is a 12-Bit Capacitive DAC. It has been taped out. The specifications below are target specifications. Check back for characterized numbers once the silicon is characterized.
| Pin name | Use | Voltage Domain | Note |
|---|---|---|---|
| avdd | analog power | 3.3-5.5V | 3.3-5.5V |
| dvdd | digital power | 1.8V | 1.8V |
| avss | analog ground | ||
| dvss | digital ground | ||
| vhigh | reference | avdd domain | avdd domain |
| vlow | reference | avdd domain | avdd domain |
| vbgsc | input voltage reference 1.024V | ||
| ena | enable | dvdd domain | dvdd domain |
| out | output | avdd domain | avdd domain |
| ibias | bandgap-controlled current bias | ||
| din[15:0] | digital input | dvdd domain | dvdd domain |
| clock | update clock | dvdd domain | dvdd domain |
| Parameter | Min | Typical | Max | Unit | Notes |
|---|---|---|---|---|---|
| Supply Voltage | 3 | 3.3 | 5.5 | V | |
| Resolution | 16 | bits | |||
| Operating Temperature Range | -40 | 25 | 85 | °C | Commercial and industrial range |
| Output Voltage Range | 0 | 5.5 | V | Rail-to-rail output (0 to V_supply) | |
| Integral Nonlinearity (INL) | 0.5 | <1 | LSB | At 25°C | |
| Differential Nonlinearity (DNL) | 0.5 | <1 | LSB | No missing codes | |
| Gain error | 10 | mV | |||
| Offset error | 10 | mV | |||
| ENOB | 15.5 | ||||
| THD | -60 | ||||
| SNR | 60 | ||||
| Settling Time | 50 | 100 | ns | To within ±0.5 LSB of final value | |
| Power Consumption | 50 | 100 | µA | Excluding load | |
| Power-Down/Disable Current | 20 | 40 | nA | When in disabled state | |
| Output Current Drive Capability | 4 | mA | |||
| Digital Input Logic Levels | 1.71 | 1.8 | 1.98 | V | Compatible with standard digital logic levels |
| Update Rate | 1 | MSPS | |||
| Temperature Coefficient | 5 | 10 | 20 | ppm/°C | |
| Startup time | 10 | µs | Time from enable to stable output |
EF_CDAC
Vendor
Efabless
130nm
Skywater
D/A Converter
Free
Open Source
EF Certified
Defined