This circuit is a 12-bit SAR ADC. It was taped out on the CI2404 Chipalooza tapeout. The specifications below are target specifications. Check back for characterized numbers once the silicon is characterized.
| Pin Name | Use | Power Domain | Notes |
|---|---|---|---|
| avdd | analog power | 3.3-5.5V | |
| dvdd | digital power | 1.8V | |
| avss | analog ground | ||
| dvss | digital ground | ||
| vhigh | reference | avdd domain | |
| vlow | reference | avdd domain | |
| ena | enable | dvdd domain | |
| dout[11:0] | digital output | dvdd domain | |
| clk | conversion clock | dvdd domain | |
| ain | analog input | avdd domain | |
| ibias | bandgap-controlled bias current | ||
| start | start conversion | dvdd domain | digital input |
| eoc | end of conversion | dvdd domain | digital output |
| Parameter | Min | Typical | Max | Unit | Notes |
|---|---|---|---|---|---|
| Supply Voltage | 3 | 3.3 | 5.5 | V | |
| Resolution | 12 | bits | |||
| Operating Temperature Range | -40 | 25 | 85 | °C | Commercial and industrial range |
| Input Voltage Range | 0 | 5.5 | V | Rail-to-rail input (0 to V_supply) | |
| Integral Nonlinearity (INL) | 0.5 | <1 | LSB | At 25°C | |
| Differential Nonlinearity (DNL) | 0.5 | <1 | LSB | No missing codes | |
| Conversion Time | 1 | µs | |||
| Power Consumption | 2.5 | 5 | mA | Excluding load | |
| Power-Down/Disable Current | 10 | 20 | nA | When in disabled state | |
| Digital control level | 1.71 | 1.8 | 1.98 | V | Compatible with standard digital logic levels |
| PSRR | -60 | -40 | dB | ||
| ENOB | 15 | bits | |||
| THD | -60 | dB | |||
| SNR | 50 | dB | |||
| Stabilization time | 100 | ns | |||
| Startup time | 50 | µs | Time from enable to start of conversion |
EF_ADC
Vendor
Efabless
130nm
Skywater
A/D Converter
Free
Open Source
EF Certified
Defined