A 32-bit Timer/Counter/Capture Soft IP in Verilog HDL. It has a generic bus interface compatible with wrapper_gen.py. Three bus wrappers are provided for: AHB-Lite, APB and WB.
You can either clone repo or use IPM which is an open-source IPs Package Manager
git clone https://github.com/efabless/EF_TCC32.gitipm install EF_TCC32| Port name | Direction | Type | Description |
|---|---|---|---|
| clk | input | Clock | |
| rst_n | input | Active low reset | |
| ctr_in | input | External events input | |
| period | input | [31:0] | 32-bit Timer Period |
| ctr_match | input | [31:0] | 32-bit match value (counter mode) |
| tmr | output | [31:0] | Current timer value |
| cp_count | output | [31:0] | Current counter value |
| clk_src | input | [3:0] | clk source (9: ctr_in, 8: clk, 0-7: clk/2 to clk/256) |
| to_flag | output | Time out flag | |
| match_flag | output | Match flag | |
| tmr_en | input | Timer enable | |
| one_shot | input | One Shot mode enable (default: periodic) | |
| up | input | Up counting enable (default: down counting) | |
| cp_en | input | External events capturing enable | |
| cp_event | input | [1:0] | External Event type (1: posedge, 2: negedge, 3: both) |
| cp_flag | output | Capture event received flag | |
| en | input | Global enable |
| mode | tmr_en | cp_en | clk_src | description |
|---|---|---|---|---|
| Timer | 1 | 0 | 0-8 | Counts clock cycles to keep track of time. - clk_src 8: clk, 0-7: clk/2 to clk/256 - up: 0: down counting (period to 0), 1: up counting (0 to period) - one_shot: 0:periodic, 1:one shot - period: starting/terminal count for down/up counting. - to_flag: is set when the tmr reaches the terminal count (up:period, down:0) |
| Counter | 1 | 0 | 9 | Similar to the Timer but it counts external pulses coming on ctr_in. match_flag is set when tmr matches ctr_match. The counting can be up/down and to/from period register |
| Event Capture | 1 | 1 | 0-8 | Capture the time between two events on ctr_in. cp_event sets the event: 1:Raising Edge, 2:Falling Edge or 3:Both. cp_flag is set when two two consecutive events are observed; once set, cp_count shows the current count. |
Reflects the status of interrupts trigger conditions detected (raw, prior to masking).
Similar to RIS but shows the state of the interrupt after masking. MIS register is always RIS & IM.
Disabling/Enabling an interrupt source.
Writing a 1 to a bit in this register clears the corresponding interrupt state in the RIS Register.
EF_TCC32
Vendor
Efabless
Timer
Free
Open Source
MIT
EF Certified
Integrated