Overview

This repo contains a 10-Bit Rail-to-Rail Digital-Analog-Converter Based-Split-Capacitive-Array titled EF_DACSCA1001

A custom digital wrapper is provided for this IP.

General Information

• Maturity: Implemented
• Certification: EF Certified
• Provider: Efabless
• License: Open Source
• Category: D/A Converter
• Foundry: N/A
• Node: N/A
• PDK: Soft IP

Prerequisites

• OS tested: Linux Ubuntu 64-bit 22.04.1-desktop-amd64
• XSCHEM V3.1.0 is a schematic capture program that provides a graphical method of the electronic schematic circuit, easily.
• NGSPICE-36 is an open-source spice simulator. It is exploited to simulate and verify the designed circuit.
• MAGIC 8.3.427 is for layout implementation and DRC checks as well.
• NETGEN 1.5.245 is used for comparing netlists of the layout and schematic, known as layout vs. schematic (LVS).
• PYTHON 3.10.12 can be integrated with the NGSPICE simulator for data manipulation/analysis of the simulation result.

Quickstart

1. Clone repo or download via IPM

   • To clone repo

   git clone https://github.com/efabless/EF_DACSCA1001.git
   

   • To download via IPM

   ipm install EF_DACSCA1001
   

2. Set environment variables

   You need to already have the PDK, you can use volare to download the pdk.

   export PDK_ROOT=<path to pdk>
   

3. Run simulation

   To run simulation go to ./verify/spice, and run these commands

   /usr/bin/time -v make verify-<test_bench>-<SIM>
   

   The test_bench is the name of the test bench for example EF_DACSCA1001_tb_func_1MHz, the SIM is either layout or schematic

   For example:

   /usr/bin/time -v make verify-EF_DACSCA1001_tb_func_1MHz-schematic
   
   /usr/bin/time -v make verify-EF_DACSCA1001_tb_func_1MHz-layout
   

   You can find all test benches that can be ran using this command

   make list
   

   NOTE: ngspice DOES NOT handle environment variables used in the test benches. the Makefile handles that for you, if you wish to use your own command make sure you manually update the spice files

1. Description

The EF_ DACSCA1001 contains an 10-bit voltage-mode digital-to-analog converter. It has a rail-to-rail output buffer and is guaranteed monotonic. The device relies on split capacitive array DAC architecture, hence low cost and fast response can be achieved. The EF_DACSCA1001 includes an enable line that acts as a power-on-reset function. The EF_DACSCA1001 is compatible with a parallel interface at a clock up to 2 MHz. The functional block diagram is presented in Figure 1.

Figure 1. Functional Block Diagram

2. Features

• Split-Capacitive Array DAC Architecture
• Low Cost and Fast Response
• 10-bit DACs with Output Follower Amplifier
• Dual Power Supply With 1.8 V, 3.3 V
• 10-bit Parallel Interface

3. Applications

• Wearable Systems
• Data Acquisition Systems
• Instrumentation and Control Systems

4. Pin Configuration and Functions

Corresponding to the Block Diagram of the EF_DACSCA1001, each pin name with its function is described in Table 1.

Table 1. Pin Configuration and Functions

5. Timing Characteristics

As depicted in Figure 2, the timing diagram of the proposed EF_DACSCA1001 is activated with an active high of EN.

Figure 2. Timing Diagram

6. Layout

Figure 8. EF_DACSCA1001 Layout.