EF_DLL_SKY130

This IP is a frequency locked Loop (ring oscillator + controller). The ring oscillator is tunable and synthesizable. The resulting netlist cannot be simulated correctly due to lack of accurate timing in the digital cell verilog models.

General Information

• Maturity: Implemented
• Certification: EF Certified
• Provider: Efabless
• License: Apache Open Source
• Category: External Oscillator
• Foundry: Skywater
• Node: 130nm
• PDK: SKY130

Installation:

You can either clone repo or use IPM which is an open-source IPs Package Manager

• To clone repo: git clone https://github.com/efabless/EF_DLL_SKY130.git
• To download via IPM , follow installation guides here then run ipm install EF_DLL_SKY130

Details

Controller

Output goes to a trimmable ring oscillator (see documentation). Ring oscillator should be trimmable to above and below maximum ranges of the input.

Input "osc" comes from a fixed clock source (e.g., crystal oscillator output). Input "div" is the target number of clock cycles per oscillator cycle. e.g., if div == 8 then this is an 8X DLL.

Clock "clock" is the DLL output being trimmed.

Algorithm:

1. Trim is done by thermometer code. Reset to the highest value in case the fastest rate clock is too fast for the logic.
2. Count the number of contiguous 1s and 0s in "osc" periods of the master clock. If the count maxes out, it does not roll over.
3. Add the two counts together.
4. If the sum is less than div, then the clock is too slow, so decrease the trim code. If the sum is greater than div, the clock is too fast, so increase the trim code. If the sum is equal to div, the the trim code does not change.

Tunable Ring Oscillator

The Ring oscillator has 13 stages, each with two trim bits delay (see above). Trim is not binary: For trim[1:0], lower bit trim[0] is primary trim and must be applied first; upper bit trim[1] is secondary trim and should only be applied after the primary trim is applied, or it has no effect.

Total effective number of inverter stages in this oscillator ranges from 13 at trim 0 to 65 at trim 24. The intention is to cover a range greater than 2x so that the midrange can be reached over all PVT conditions.

Frequency of this ring oscillator under SPICE simulations at nominal PVT is maximum 214 MHz (trim 0), minimum 90 MHz (trim 24).

Frequency of this ring oscillator measured on silicon is maximum 113.35 MHz (8.8ns) and minimum 50.25 MHz (19.9ns). The maximum and minimum rate equations are:

• max rate = 1/(4 * delay0)
• min rate = 1/(4 * (delay0 + delay1 * 26))

Installation:

You can either clone repo or use IPM which is an open-source IPs Package Manager

• To clone repo: git clone https://github.com/efabless/EF_DLL_SKY130.git
• To download via IPM , follow installation guides here then run ipm install EF_DLL_SKY130