EF_QSPI_XIP_CTRL

Quad I/O SPI Flash memory controller with support for:

• AHB lite interface
• Execute in Place (XiP)
• Nx16 Direct-Mapped Cache (default: N=32).

Intended to be used with SoCs that have no on-chip flash memory.

General Information

• Maturity: Integrated
• Certification: EF Certified
• Provider: Efabless
• License: Apache Open Source
• Category: SPI
• Foundary: N/A
• Node: N/A
• PDK: Soft IP

Performance

The following data is obtained using Sky130 HD library

AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP.

The wrapped IP

The IP comes with an AHBL Wrapper

Wrapped IP System Integration

EF_QSPI_XIP_CTRL_APB INST (
        `TB_AHBL_SLAVE_CONN,
        .sck(sck),
        .ce_n(ce_n),
        .din(din),
        .dout(dout),
        .douten(douten)
);

NOTE: `TB_APB_SLAVE_CONN is a convenient macro provided by BusWrap.

Implementation example

The following table is the result for implementing the EF_QSPI_XIP_CTRL IP with different wrappers using Sky130 PDK and OpenLane2 flow.

The Interface

Ports

Installation:

You can either clone repo or use IPM which is an open-source IPs Package Manager

• To clone repo: git clone https://https://github.com/shalan/EF_QSPI_FLASH_CTRL
• To download via IPM , follow installation guides here then run ipm install EF_QSPI_XIP_CTRL

Run cocotb UVM Testbench:

In IP directory run:

cd verify/uvm-python/

To run testbench for design with APB

To run all tests:

make run_all_tests BUS_TYPE=APB

To run a certain test:

make run_<test_name> BUS_TYPE=APB

To run all tests with a tag:

make run_all_tests TAG=<new_tag> BUS_TYPE=APB

To run testbench for design with APB

To run all tests:

make run_all_tests BUS_TYPE=AHB

To run a certain test:

make run_<test_name> BUS_TYPE=AHB

To run all tests with a tag:

make run_all_tests TAG=<new_tag> BUS_TYPE=AHB

Todo:

• Add support for WB bus
• Support cache configurations other than 16 bytes per line