Netgen is a tool for comparing netlists, a process known as LVS, which stands for "Layout vs. Schematic". This is an important step in the integrated circuit design flow, ensuring that the geometry that has been laid out matches the expected circuit. Very small circuits can bypass this step by confirming circuit operation through extraction and simulation. Very large digital circuits are usually generated by tools from high-level descriptions, using compilers that ensure the correct layout geometry. The greatest need for LVS is in large analog or mixed-signal circuits that cannot be simulated in reasonable time. Even for small circuits, LVS can be done much faster than simulation, and provides feedback that makes it easier to find an error than does a simulation.
Netgen version 1.5 is considered complete and competitive with commercial-grade tools. Code was added to handle device properties and to resolve parallel combinations of devices whether individually instantiated or implied through the use of the "M" property. Serial and parallel networks of passive devices are analyzed and compared between networks.
Netgen was written by Massimo Sivilotti and later Tim Edwards incorporated it into the Tcl-based suite of tools including magic, IRSIM, and xcircuit.
All things Netgen including installation information, release notes, code history, references, and tutorials can be found here.
The OpenCircuitDesign download can be found here.
To access the Open Circuit Design Git repository holding the most recent netgen source execute
git clone git://opencircuitdesign.com/netgen
or use the GitHub mirror site:
git clone https://github.com/RTimothyEdwards/netgen
NETGEN LVS
Community
Tim Edwards
Analog & M/S EDA
Free