• Developed a new Reduced Instruction Set with least possible no. of instructions in it such that the designed Processor can be used to implement almost any Function by combination of instructions
• Using the concept of pipelining divided execution of instruction into three stages such that effectively one instruction is executed for every clock cycle
• It is developed for understanding the micro-architecture and ways to develop a processor by students

There is no intention to copy or mimic any existing processor.

I would like to thank NSDCS lab IIT Indore ( https://sites.google.com/site/svishvakarma/home ), especially prof. Santosh K Vishvakarma and Radheshyam ( https://in.linkedin.com/in/radheshyam-sharma-37aa3713b ) for helping me and letting me know about this opportunity.