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HyperRAM controller
public project

This project makes additional, external HyperRAM memory (Cypress S27KL0641 8MB or similar) accessible to SoC via Wishbone bus.

Functionality implemented inside HyperRAM driver / limitations:

  • working with wb_clk_i clock (external HyperRAM clock is two times smaller due to DDR)
  • read and write to both memory and register space (inside HyperRAM chip)
  • single 32 bit access to memory space (no burst)
  • single 16 bit access to register space (inside HyperRAM chip)
  • adjusting timings (tacc, tcsh, tpre, tpost and read timeout) possible via registers (accessible via Wishbone)
  • fixed latency (1x/2x) or variable latency (according to RWDS signal state during CA phase) - configurable in register
  • read timeout in case of external HyperRAM connection failure

Project instantiates HyperRAM controller for external memory chip (8MB version) connected to management SoC via Wishbone bus.