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Pyramiden Core
public project
GFMPW-0   
Organization URL

www.browndeertechnology.com

Description

This is a processor design that evolved from a tiny tapeout submission. The core implements a reduced ISA based on RISC-V supporting 16-bit data and memory operations with 21-bit instructions. The full RISC-V base instruction set is supported with the exception of the CSRs, and the core has 16 registers.

Version

1.0

Process

gf180mcuC