The "AFTx06_Caravel" repository is the collection of files for the AFTx06 RISC-V core that was designed by the Purdue System-on-Chip Extension Technology (SoCET) team. As an undergraduate team, our goal is to provide students with an educational hands on experience for system-on-chip (SoC) design with industry quality SoC design flows. Within the greater SoCET team, there are six well defined sub-teams: Digital Design, Verification, Software, PCB Design, Physical and Analog Design, and Design Flow. Within the six sub-teams, there are groups of students working on peripheral components or small projects, for example of which, many students develop a project within SoCET for their senior design projects. The results of their experiences are reflected within the design for the AFTx06. Being the sixth iteration of the Purdue SoCET team's SoC design, the AFTx06 improves upon our previous design, the AFTx05. The AFTx06 improves upon the previous iteration through additional features such as an added M-Extension, Local and External Interrupt Controller, redesigned Master MUX that now includes Formal Verification, as well as SPI and I2C capabilities. A complete list of the included modules/peripherals is given in the Features section.


As undergraduates, members of the Purdue SoCET team are able to engage in RTL, Physical, and PCB design; chip bringup; verification methods; and various EDA tools and software suites. This allows a student through SoCET to engage with the entire life cycle of chip design even as an undergraduate with any degree of prior experience. The AFTx06 thereby represents the combined efforts of the team and its consultants through multiple years of research and design in developing a successful RISC-V core that can be used for low power IOT devices, edge node computation, or machine learning applications thanks to the implementation of a SparCE Architecture within our design.


The AFTx06 implements an RVIMF Instruction Set, with Multiplication and Division capabilities, as well as other unique features and abilities that are not commonly found on other SoC devices. Arguably the most intruiging feature is the SparCE Machine Learning Architecture, an on-chip machine learning architecture to utilize sparsity in convolution arithmetic, allowing extraneous instructions to be skipped. More details on the SparCE architecture is given in the SparCE Machine Learning Architecture section found under Features, below. The AFTx06 also includes novel and experimental designs such as Non-Symmetric CMOS Implementation of Polymorphic Logic, Layout for Electromigration Test Structures, JTAG interface, Phase-Locked Loop, and Platform-Level Interrupt Controller. Many features are experimental designs put forth by Purdue University professors and implemented by the SoCET team. Further details on these can be found in sections below of the same names.

Figure 1: AFTx06 Block Diagram

List of Current Features (Modules/Peripherals):

  • 32kHz Ring Oscillator
  • APB
  • AHB - APB Bridge
  • AMBA 3.0 AHB-lite Bus
  • GPIO
  • I2C
  • PLIC
  • RISC-V Processor (1st AHB Primary Device)
    • RV32I Instruction Set Architecture
    • Pass Through Cache
    • 2 Stage Pipeline
  • SPI
  • UART Debugger (2nd AHB Primary Device)

Memory Map:

Address Range Size (Used) Unit
0xFFFF-FFFF ... 0xF000_0000   Reserved
0xEFFF_FFFF ... 0xE001_0000   Reserved
0xE000_FFFF ... 0xE000_0000   Interrupt Controllers Clint - # of Address depends on # of cores (1 core - 20 bytes) PLIC - # of addresses depends on # of external interrupts
0x9000_FFFF ... 0x9000_0000 8 Bytes SparCE SASA Table Offset 0x00: Write addr for SASA entries Offset 0x04: Write addr for SASA config
0x8FFF_FFFF ... 0x8005_0000   Reserved for other peripherals
0x8004_FFFF ... 0x8003_0000   I2C
0x8003_FFFF ... 0x8003_0000   SPI
0x8002_FFFF ... 0x8002_0000   Timer
0x8001_FFFF ... 0x8001_0000   PWM
0x8000_FFFF ... 0x8000_0000   GPIO
0x7FFF_FFFF ... 0x0020_0000   Reserved
32'h001F_FFFF ... 32'h0000_8400 2MiB (Initial 33792 bytes unused) Main Memory for the SoC
32'h0000_83FF ... 32'h0000_8000 1024 bytes Onchip RAM "TOP RAM"
32'h0000_7FFF ... 32'h0000_0200 32256 bytes Onchip self test ROM
32'h0000_01FF ... 32'h0000_0200 480 bytes Reserved
32'h0000_001F ... 32'h0000_0000 8 words (16 bytes) Address 0x00 = PC to jump to after debugger writes "BOTTOM RAM"

SparCE Machine Learning Architecture

Figure 2: SparCE Block Diagram

SpareCE is an on-chip machine learning architecture that utilizes sparsity in convolution arithmetic to allow extraneous instructions to be skipped. Utilized by our design, the architecture has been designed to improve both the speed and power consumption of this common machine learning calculation. Students Vadim Nikiforov and Chan Weng Yan designed the module as it was described in the paper SparCE: Sparsity Aware General-Purpose Core Extensions to Accelerate Deep Neural Networks [1] with the intent to demonstrate the capabilities of the architecture on an ASIC implementation.

Figure 3: SparCE Diagram Architecture

The design architecture of the SparCE module is shown in Fig. 3. The blocks within the dotted boundary illustrate the interaction between functional blocks. Signals outside the boundary are inputs from and outputs to the rest of the pipeline.

  • The Sparsity Register File (SpRF) is used to dynamically track which registers in the processor’s register file contain zero values. The SpRF contains one entry corresponding to each register in the register file.
  • The Sparce Value Checker (SVC) checks if the value is zero and updates the SpRF correspondingly, when an instruction that writes to a register completes,
  • The Sparsity Aware Skip Address (SASA) table is a cache-like block with associative memory structure which stores the information required to skip a region. Each entry contains the PC of the instruction prior to the skippable region, a field which stores the condition for the region to be skippable, and the number of instructions that can be skipped.
  • The Pre-identify and Skip Redundancy Uni (PSRU) uses the SASA table to identify and skip redundant instruction regions. For each instruction, we check if its PC contains an entry in the SASA table. An entry in the SASA table indicates that the instruction following the current instruction is the start of a potentially skippable region. In this case, the PSRU checks the SpRF to identify if the registers indicated in the SASA table entry are currently zero. If so, it increments the PC to the end of the redundant instruction sequence, thereby skipping instructions. If not, the pipeline proceeds to execute instructions in program order.
  • The Control Flow Instruction Detector (CFID) decodes the instruction in the decode stage rather than waiting for the instruction to be decoded in the execute stage. This allows control flow instructions to have higher precedence than skipping.

Platform-Level Interrupt Controller

The Platform-Level Interrupt Controller (PLIC) is a standard interrupt management protocol for managing timer, software, and external interrupt communications by reading a memory-mapped register. The interrupt controller will be included in AFTx06, the next chip that SoCET will tapeout. It should be noted that there are different priority levels for different user modes (U, S, H, M). Currently, M mode (or machine mode) is the only privilege level being configured because this is a mandatory privilege level for the hardware platform. The PLIC takes in hardware interrupt requests and serves them, along with an interrupt ID, to the processor. The Interrupt Controller is currently built for an address width of 32 bits and stores information in 32-bit registers

Figure 4: Top Level Communications Between PLIC, the External Modes, and the Processor

The Interrupt request registers translate hardware interrupt requests into pulses to be sent to other components in the submodule. Register mask prevents masked interrupts from triggering an interrupt request. The interrupt enable register handles logic controlling which registers are masked; it handles status registers related to masking individual interrupts as well as interrupt masking when the disable low priority interrupts module is enabled. The interrupt pending and priority registers module handle registers controlling interrupt priorities as well as the interrupt pending registers. The interrupt priority registers indicate the priority of each hardware interrupt channel and the interrupt pending registers indicate which registers are in the queue to be serviced. The interrupt priority resolve register handles sending the highest priority interrupt index to the status registers for the CPU to read.






Google SkyWater PDK


Currently, Yosys cannot synthesize the source code because some of our packages cause issues. As a result, the design must be first put through Genus for synthesis, continuing with the rest of the design flow process after obtaining a synthesized netlist.

Thus, in order to synthesize the design, the user can follow the resulting steps within the command terminal.

make user_project_wrapper


Figure 5: Placement Layout of the AFTx06

Future Work

In the future, once the team obtains the fabricated AFTx06 we plan on utilizing an SoC Tester, the Agilent 93000 SOC Series Test System, to test and verify our design under real environmental conditions. Testing will occur locally and be performed by undergraduate members of the Purdue SoCET Team. From testing, we hope to obtain further metrics about our design and analyze how it performs, in order to improve our design for the chip's next iteration.


A working design was generated through the efforts of current and former Purdue SoCET team members and consultants over the last several years. We would like to thank the Doctors Raghunathan, Appenzeller, and Bermel for their contributions to the SparCE architecture, Polymorphic CMOS, and Electromigration Test Structures, respectively.


[1] S. Sen, S. Jain, S. Venkataramani and A. Raghunathan, "SparCE: Sparsity Aware General-Purpose Core Extensions to Accelerate Deep Neural Networks," in IEEE Transactions on Computers, vol. 68, no. 6, pp. 912-925, 1 June 2019, doi: 10.1109/TC.2018.2879434.

[2] S. Das and J. Appenzeller, "WSe2 field effect transistors with enhanced ambipolar characteristics," Applied Physics Letters 103, 103501-1-5 (2013).

[3] C. Cummings, “Simulation and Synthesis Techniques for Asynchronous FIFO Design,” Sunburst Design, Provo, UT, USA, 2002.

[4] JTAG Programmer Overview for Hercules-Based Microcontrollers, Texas Instruments, Dallas, TX, United States, Nov. 2015, Accessed on: September, 4th, 2019. [Online]. Available: https://www.ti.com/lit/an/spna230/spna230.pdf


The SkyWater Open Source PDK is released under the Apache 2.0 license Apache 2.0 license. The copyright details (which should also be found at the top of every file) are

Copyright 2020 SkyWater PDK Authors Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

If you are collaborating on this project, please click here to access your collaboration files, and click "Accept Share" in the actions column if you haven't done so already.

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John Martinuk


Purdue's University's Socet Undergraduate Team Creates Soc's, Aimed To Be Integrated Into Low Power Iot Systems. This Architecture Includes A Sparce Structure That Improves Latency And Power Consumption Of Convolutions Often Used In Ml Algorithms That Utilize Relu Functions. It Does This By Skipping Instructions That Will Have A Product Of Zero.





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07/22/21 07:32:35 PDT