Description:
This project is the extended version of Azadi-SoC, which includes all of the peripherals which were in Azadi-I and few more this time, which were not stable at the time of Azadi-I. Azadi-II is also a final year project of undergrad students.
The Azadi-II includes the following peripherals.
Design Goals:
Azadi-II is aimed to extend the base ibex core(RV32IMC) with a fully functional single precision floating point unit and RISCV compliant debug module for on chip debugging and some standard peripherals for communicating with other devices. all these modules will be interlinked using standard Tilelink Bus protocol.
Target Performance:
for Azadi-II frequency is the main performance parameters. The target is to achieve 40MHz of sign-off frequency. In the previous version the frequency was about 25MHz.
Block Diagram:
Language: SystemVerilog.
References:
[1] https://github.com/lowRISC/ibex
[2] https://github.com/lowRISC/opentitan
[3] https://github.com/pulp-platform/riscv-dbg
Team Members:
1) Zeeshan Rafique (undergrad student, computer systems engineering, UIT).
2) Sajjad Ahmed (undergrad student, computer systems engineering, UIT).
3) Muhammad Waleed Waseem (undergrad student, computer systems engineering, UIT).
4) Usman Zain (undergrad student, computer science, UIT).
5) Zain Rizwan Khan ( design verification engineer, Microelectronics Research lab).
6) Rameen Anwar (physical design engineer, Microelectronics Research lab)
7) Aireen Amir Jalal (physical design engineer, Microelectronics Research lab).
8) Dr. Ali Ahmed (Project supervisor, team lead Microelectronics Research Lab.
9) Dr. Roomi Naqvi (Director of Microelectronics Research Lab).
Azadi-II is the extended version of AzadiI which is an SoC based on RISCV RV32IMCF architecture. it uses ibex_core as its central processing unit with additional single precision floating point extension, and peripherals for out world communication.
processor