Description
The idea is to design an accelerator, for Ternary Content Addressable Memory (TCAM) by using Static Random Access Memory (SRAM) macros. The plan is to utilize OpenRAM compiler to compile SRAMs, which mimic the functionality of TCAM, with auxillary logic circuits.
Design Goals
TCAM Accelerator IP: This TCAM accelerator will be MMIO to the management SoC (Caravel- harness) and will be act as accelerator for TCAM functionality.
We will utilized already genrated SRAM blocks generated using OpenRAM compiler. In this project, we are utilizing 1 KB SRAM block to generate 32x8 bit and other size TCAM blocks.
It will provide single/multiple cycle search operation.
It include additional priority encoder
It has additional logic circuity with SRAM.
Block Diagram
Reference:
https://ieeexplore.ieee.org/document/7797247
Team Members:
1. Sajjad Ahmed (Undergraduate student , Computer Engg, Usman Institute of Technology)
2. Zeeshan Rafiq (Undergraduate student , Computer Engg, Usman Institute of Technology)
3. Hafiz Wajeeh (Research Associate -MERL-UIT)
4. Hadir Khan (Research Associate -MERL-UIT)
5. Ali Ahmed (Assistant Professor - UIT, Team Head- MERL-UIT)
6. Syed Roomi Naqvi (Adjunct Professor- UIT, Director MERL)
7. Matthews Guthaus , Prof. University of California Santa Cruz - VLSI Design automation Lab- OpenRAM Compiler.
This project is tied as an accelerator to the management SoC. It mimic the functionality of TCAM using SRAM. We will utilize OpenRAM to compile SRAM-based TCAM.
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