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Lexicon_SoC

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Description

This project aims to design a fully functional SoC which holds the SweRV-EL2 Core, AXI interconnect, AXI2APB Bridge, UART, I2C, GPIO, PWM, Timer and SPI

Design Goals

The purpose of this project is to convert the SweRV-EL2 Core Complex into SoC by adding peripherals around it using ABP protocol. The verification of this project will be done by using UVM.

This is a final year project of undergraduate students

Tools: Cadence suite.

Language: SystemVerilog + Verilog

Block Diagram:

References:

https://github.com/chipsalliance/Cores-SweRV-EL2.git

https://fabrics.readthedocs.io/en/latest/overview.html

https://github.com/ZipCPU/wb2axip.git

Team Members: Marium, Rehan, Uzair, Wishah, Kinza, Wajeh, Dr. Salman, Dr. Ali, Dr. Roomi.

 

If you are collaborating on this project, please click here to access your collaboration files, and click "Accept Share" in the actions column if you haven't done so already.

Owner

Marium Masood

Summary

This project aims to convert the SweRV-EL2 Core Complex into SoC by adding peripherals around it using ABP protocol. The verification of this project will be done by using UVM. Specification: The SoC holds the following SweRV-EL2 Core AXI interconnect AXI2APB Bridge UART I2C GPIO PWM Timer SPI

Version

2

Category

processor

Process

sky130A

Shuttle Tags

SSCS-21