Description:

A pipelined-flash ADC architecture and an encoder (DCVSPG encoder) for high-speed flash CMOS ADC is proposed. The pipelined architecture achieves high data throughput and high speed by incorporating pipelined clocked T/H and clocked DCVSPG encoders.

The flash ADC uses a differential architecture in designing the comparator to minimize the input-offset voltage error. The comparator uses the technique of generating the reference voltages internally and eliminating the use of the resistor ladder circuitry.

As a result, improvements on the nonlinearity error and power saving are achieved. The pipelined flash ADC offers a data conversion rate of 2.5 GSPS while maintaining low power consumption, which makes it suitable for SoC applications.

FFT tests with input signal frequency up to 1 GHz prove proper operation over a wideband frequency range. The DCVSPG encoder overcomes the speed limitation of the ROM encoder which has been a bottleneck of high-speed ADCs

Design Goals:

VDD: 1.2 V

Resolution: 4-Bit

V_LSB = 0.025V

Sampling Rate: 2.5 GSPS

Input Signal Frequency: Upto 1GHz

Power <= 25 mW

Block Diagram:

Schematics:

T/H Circuit:

Cascade Current Source:

Differential Comparator:

References:

M. Wang, C. H. Chen and S. Radhakrishnan, "Low-Power 4-b 2.5-GSPS Pipelined Flash Analog-to-Digital Converter in 130-nm CMOS," in IEEE Transactions on Instrumentation and Measurement, vol. 56, no. 3, pp. 1064-1073, June 2007, doi: 10.1109/TIM.2006.887404.

Team Members:

1. Aditya Sharma (Lead Designer)

2. Vatsal Dixit