Description:

An efficient 1kb SRAM 8x4 Cell array, built on 32-bit 7T SRAM Cells, in which a novel 7T SRAM design is utilized, which offers better stability and low leakage over conventional design. This was achieved using high Vth pull-up PMOS and extra one NMOS transistor.

Why we decided on this?:

Even today, SRAM is the fastest semiconductor memory devices, utilized in building CPU Cache memories for High-end devices. But, as modern era demands high performance and low-power, for wearables and handsets, which can't be fulfilled by a conventional design due to high leakage currents and less stability. So, we wanted to come up with a new circuit, which exhibits better stability and lower leakage currents, thus delivering high-end device requirements.

Design Goals:

1. To design an efficient 1kb SRAM, which can operate at high clock speeds, and exhibit low leakage.
2. To improve the read/write stability under large variations.
3. To prevent the conventional half-selection issue.

Block diagram of our Design:

Figure 1: 16-bit SRAM sub-array

Figure 2: 32-bit SRAM Sub Array

       A 32b SRAM Sub Array is constructed by using 16 bit 7T SRAM cells. This sub Array has the capability to store 2⁵ bits. This can be accomplished by using an (1-2) word line decoder and (2-1) Multiplexer, as shown in Figure 2.

16b = 2⁴b

32b = 2⁴ b x 2¹ b = 2⁵b

 1 kb Sub Array:

       A 1-kb Sub-Array can be built as 8 rows Χ 4 columns. An SRAM 1-kb Sub-Array is designed with the help of 32 bit Sub-Array. In order to address one row out of 16, the row address decoder needs 5 address bit i.e. 2⁵ bits = 32 bits.

Figure 3: 1 kb SRAM Cell Array

This can be accomplished by using (3-8) row address decoder and (2-4) column address decoder. 1kb Sub-Array is shown in Figure 3.

32 bits = 2⁵ bits

1kb = 2⁵ x 2³ x 2² bits = 2¹⁰ bits

Schematics:

Figure 4: Basic 7T SRAM cell

Figure 5: Basic 7T SRAM Cell array

Expected Performance Summary of 7T SRAM Cell (130nm process):

References:

1. SRAM Circuit Topologies: https://drive.google.com/file/d/1ZGnr-peAYKCfvxOGbznfdm8cwIVCjIym/view?usp=sharing
2. Aly, R. E., Faisal, M. I., & Bayoum, M. A. (2005). Novel 7T SRAM cell for low power cache design. IEEE International Conference on SOC, 171–174. doi:10.1109/SOCC.2005.1554488 [Crossref], [Google Scholar]
3. A. Kotabe et al., "A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme," in IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 870-876, April 2005, doi: 10.1109/JSSC.2005.845553.

Team Members:

K. Sarath Chandra (College Faculty Mentor)

Lakku Yashaswi (Lead Designer)

Kothapalli Srujana

Kummari Shivani

Kuruva Thirumalesh