Inductor Less Bi-Directional Amplifier for 5G Applications

Motivation

5G is an emerging communication technology, which promises higher data rates and lower latency. 5G technology utilizes MIMO architectures to optimize beamforming and reduce interference. MIMO architectures consist of multiple transmitter and receiver chains as shown in Figure 1. For on-chip cost effective solutions, power and area of individual RF components must be optimized. One such component is low noise amplifier (LNA) of receiver. LNA is a critical component because it dictates the noise figure of the entire receiver chain. Lower noise figure means higher receiver sensitivity. For MIMO systems, a low noise amplifier should have following specifications:

1. Low Noise Figure (Better Receiver Sensitivity)
2. Low Silicon Area (Cost Effective)
3. Low Power (Longer Battery Life)
4. Wide Band (Higher Data Rate / Multiple Communication Standards)
5. High Linearity
6. Input Matching (at 50 Ohms)

Proposed Circuit

LNA utilizes on-chip inductors for gain peaking and input matching. However, inductors occupy large silicon area. An inductor-less LNA design saves huge area and enables wide band operation since no sharp resonance is present. Noise figure can be reduced by feedback and feed forward techniques. The schematic of the proposed inductor less LNA is shown in Figure 2. This design is inspired from this ISSCC paper [1].

This design has several features. It achieves wide band input match using transistor M4. The size of M4 required for matching is also reduced due to feedback. The gain of circuit is increased by current reuse (M1) and cascode technique (M2). Partial thermal noise of transistors M0, M1 and M2 is cancelled using the feedback. In [1], the noise contribution of M4 is not cancelled. In the proposed design, the noise figure of M4 is also cancelled using feed forward noise cancellation technique (M6-M7). Usually, feedforward technique introduces additional noise figure due to the parallel feed forward path [2]. However due to the inherent parallel path, no extra noise at input is introduced. Also, the voltage at Vo- gives extra gain without any power consumption as compared to [1]. The proposed modifications can result in decreased noise figure and increased voltage gain in the same area and power. The target specifications of the proposed design are summarized in Table 1.

Table 1 Target Specifications

Team

1. Engr.  Shahid Jamil (i201304@nu.edu.pk)
2. Prof. Dr. Rashad Ramzan (rashad.ramzan@nu.edu.pk)
3. Dr. Hassan Saif (hassan.saif@nu.edu.pk)

Deliverables

Schematic, Layout, GDS, Measurement Results, Design Report

References