XOR Physical Unclonable Function (XOR PUF)
This is a design for SSCS chip Ignite 2021. In this project, we will develop XOR PUF model.
Background
In recent years, we have consider the massive production of mobile and embedded devices in daily tasks. Many tasks require securely authenticate by 3rd parties or/and securely handle private information. There are vary ways to develop software authenticate, however such many devices have to operation in untrusted environment and adversary have ability to physically access to devices. There are several method to secure the private information and authenticate by using EEPROM and SRAM, but these methods have cease the price of device. Physical unclonable functions (PUFs) have advantage in authentication and secret key storage without the expensive hardware.
Our XOR PUF design model based on Arbiter PUFs. The idea behind Arbiter PUFs is to race the delay times between two signal. Two signals are guilded by the challenge inputs and connect to enable and delay terminal of D flip flop. Process variation introduced during IC manufacturing causes the different delay for each signal, as a result the output of D flip flop will be ‘1’ or ‘0’ depending which signal arrives D flip flop first. The outputs of APUF blocks will be connected to the XOR gate to get the final output.
Our design
We propose a design of an 64bit XOR PUF.
Arbiter PUF 64bit
XOR PUF
Members
Anh - Phan Minh: Inplement, layout
Minh - Truong Cong: RTL code, testing, layout
Tu - Phan Anh: RTL code, testing, layout
Anh - Dang Le Trong: Implement, layout
Hieu - Duy Bui: Advisor
Reference
Herder, C., Yu, M.-D., Koushanfar, F., & Devadas, S. (2014). Physical Unclonable Functions and Applications: A Tutorial. IEEE, 102(8).