Openlane RTL to GDSII flow we have implemented works well for digital synthesis and chip assembly for the test case picorv32 RISC V core. While digital synthesis flows are powerful and go hand in hand with open source designs in hardware description languages. The methodology was implemented using Sky-
Water and open source PDK. The results at various stages are steamed out using klayout and finally GDSII file is obtained that the Foundries accept for the manufacture of ASICs.Open-source EDA is truly a field of dreams, it goes beyond academic research skillsets and hence is part of a movement.
If you are collaborating on this project, please click here to access your collaboration files, and click "Accept Share" in the actions column if you haven't done so already.
This project mainly performs the full ASIC implementation of the design from RTL to GDSII. RISC-V is described as a specification and Picorv32 is the RTL implementation of that specification.