Block Diagram:

(a)	(b)
Fig. 1 (a) A conceptual diagram of a general skew based voltage controlled oscillator (VCO) (b) pre-charge discharge skew based delay cell

Schematics:

Fig. (c) Connection mechanism for the design of 5-stage NSO based voltage controlled ring oscillator

Fig. (d) The simulated waveform of the 5-stage NSO based VCO in which noise suppression mechanism is observed at 1 MHz offset.

Description:

Modern communication systems are evolving continuously and increasing exponentially and require high-performance and low-noise oscillators within the allowed power budget. Oscillators are critical components of communication systems and processors since they ensure that all data flows are accurately synchronized and/or modulated. Therefore, a high-performance (with an oscillation frequency equivalent to a 3-stage conventional RO (CRO)) oscillator equipped with noise suppression, wide tuning range, and asymmetric/symmetric load/driver skew-based VCRO is proposed for the first time. This architecture is a potential candidate to provide possible solutions for some frequently encountered design issues in oscillator design. It also serves as a preferable candidate for the design of a VCO-based ADC, especially when a large number of RO  stages are required. The proposed design not only ensures an oscillation frequency equivalent to that of a 3-stage CRO but also ensures a large number of stages in the design. Also, it can be employed in generating multiphase signals through injection locking techniques/frequency synthesizers.  

The VCO delay-cell stage is a combination of a skew-based inverter proposed in [1]  and additionally designed top/bottom drive circuits to achieve symmetrical variation in output transitions, as shown in Fig. (a). It consists of 3 main sub-blocks:

1) Block A: Biasing Circuit, consisting of diode-connected transistors (M_{P_CB}, M_{N_CB})

2) Block B: Delay Cell core, consisting of a top drive (M₁₁, M₁₂), a bottom drive (M₂₁, M₂₂), and the skew-based inverter core (M_P, M_N)

3) Block C: Level Shifter, basically, a Common Source Amplifier consisting of (M_{P­­_LS}, M_{N_LS})

The control voltage signal (V_control) is provided to the NMOS transistor, which drives the output falling transition (M₁₂), while a signal of (V_dd – V_control) is provided to the PMOS transistor, which drives the output rising transition (M₂₂), with a Common Source Amplifier (CSA) to map the signal V_control to (V_dd – V_control). The transistors M₁₁ and M₂₁ are based at fixed drain currents I_{P_FIX} and I_{N_FIX} by appropriately sizing diode-connected transistors M_{P_CB} and M_{N_CB,} respectively. A  variation in V_control results in a variation in the transistor currents I_{N_Cont} and I_{P_Cont}, which alters the discharging/charging rate of the total output capacitance (C_P+C_L). This is the essence of the frequency control mechanism for our design, similar to the one in [3]. The core delay cell (Block B) can be replaced by Blocks equipped with Pre-charge(PC)/Pre-discharge(PD) transistors (M_PC/M_PD) through feedforward techniques for symmetric output transitions, as shown in [2]. Additionally, fine-tune transistors M_{P_FT} and M_{N_FT} are introduced in series with the PC/PD transistors to exercise control over the base output rise/fall transition times and the voltage sensitivity by adjusting another control input V_{FINE_TUNE}, as shown in Fig. (b).

The individual single-ended delay cells outputs and inputs are connected to each other to form NSO/PSO architectures, resulting in (3N-1)/(3N+1) number of VCRO stages, as shown in Fig. (c). As explained in [1], N 3-stage coupled oscillator loops function out of phase to produce a sustained switching output waveform, oscillating at a frequency nearly equal to the one generated by a 3-stage CRO.    

The proposed VCO architecture exhibits a fixed phase noise profile for a specific offset frequency, even when V_control is varied across a significant portion of its tuning range. This property is not delayed cell-dependent and is valid for any input skew, even when the skew is reduced to 0. Considering a case when V_cont is given directly to M₁₂ and fed through a CSA for M₂₂,  phase noise remains fixed with V_control till it rises up to a critical value (V_critical), for an output frequency f_critical. The phase noise at the output is suppressed primarily because of strong attenuation at voltages below the critical control signal and corresponding frequencies higher than f_critical. At frequencies lower than the critical frequency, however, the magnitude of the delay cell shaping function allows phase noise at the input to appear at a delay cell's output with minimal attenuation, resulting in a noticeable spike in phase noise, as shown in Fig. (d)

Design Goals:

• Highest achievable base frequency (equal to that of a 3-stage CRO)
• Wide tuning range (0 to V_dd)
• Nearly constant phase noise over the entire tuning range
• Improved linearity

Target Performance Summary:

Tuning Range: 0 to V_dd

Phase Noise: Constant over V_control for any number of stages.

References:

[1] N. Mishra et al., "Design and Realization of High-Speed Low-Noise Multi-Loop Skew-Based ROs Optimized for Even/Odd  Multi-Phase Signals," IEEE Trans. Circuits Syst. II: Express Briefs, vol. 67, no. 11, pp. 2352-2356, Nov. 2020".

[2] N. Mishra et al., "Delay Modulation in Separately Driven Delay Cells Utilized for the Generation of High-Performance Multiphase Signals Using ROs," in IEEE Transactions on Circuits and Systems II: Express Briefs, doi: 10.1109/TCSII.2021.3081829.

[3] B. Razavi, Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level. Cambridge: Cambridge University Press, 2020.

Team Members:

Anchit Proch, Neeraj Mishra, Prof. Anand Bulusu

Microelectronics and VLSI Group, Department of Electronics and Communication Engineering, IIT Roorkee, India.