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Caravel
public project
MPW-1

N5 SoC for Caravel

The repo contains the N5 SoC integratin with the Caravel chip. For the SoC related development, refer to N5 SoC

Caravel Integration

Verilog View

The SoC utilizes the caravel IO ports and logic analyzer probes. Refer to user_project_wrapper.v and this.

GDS View

If you are collaborating on this project, please click here to access your collaboration files, and click "Accept Share" in the actions column if you haven't done so already.

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Organization URL

http://efabless.com

Summary

NFive32-Based SoC to validate several open-source projects and IPs.

Version

1.00

Process

sky130A