LOGIC BIST Block Diagram

Key features

    * Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
    * Mbist controller with memory repair supported
    * LOGIC BIST with 8 Scan-in/Scan-out chain
    * Wishbone compatible design
    * Written in System Verilog
    * Open-source tool set
       * simulation - iverilog
       * synthesis  - yosys
       * backend/sta - openlane tool set
    * Verification suite provided.

Prerequisites - Tools

There are hacks are done in openlane script/tool to integrated the scan chain. The tool and scripts are updated in dineshannayya:mpw4 docker. Here are details on hacks:

Hack-1: Added DFF to Scan for replacement function

   Directory: OpenSTA (hacks/src/OpenSTA)
   Source Files:
	   hacks/src/OpenSTA/network/ConcreteNetwork.cc
	   hacks/src/OpenSTA/tcl/NetworkEdit.tcl
	   hacks/src/OpenSTA/tcl/Sta.tcl
    Patch File: for OpenRoad docker
           hacks/patch/scan_swap.patch

Hack-2: Patch to disable Manually inserted delay cell resize

   Directory: OpenROAD
   Source Files:
           hacks/src/OpenROAD/Resizer.cc
    Patch File:  for OpenRoad docker
           hacks/patch/resizer.patch

Hack-3: Manual Pin Placement Option

   Directory: Openlane
   Source Files:
           hacks/src/openlane/io_place.py

Hack-4: Synthesis Parameter Over-ride option added with ENV : SYNTH_PARAMS

   Directory: Openlane
   Source Files:
           hacks/src/openlane/synth.tcl
           hacks/src/openlane/synth_top.tcl

all these hacks/patches are implemented inside dineshannayya:mpw4 docker

Prerequisites - Design

for logic bist to work properly, design should met these crieria.

Clock Doman: All the Sub block should be synchronous and use single clock
Reset: Scan Reset Bypass logic need to implemented
SRAM: SRAM input towards digital logic should have scan bypass
Register: All the Register should be able to re-initialize with reset, even the two dimensional FIFO.
Input: All the Input should be in known state, else add scan bypass logic

Layout Image

Owner

Dinesh Annayya

Description

Logic BIST with Scan Chain to detect struck at fault

Git URL

https://github.com/dineshannayya/logic_bist.git

Version

Process

sky130A

Labels

LBIST

MBIST

SCAN