This project is the extended version of Azadi-SoC, which includes all of the peripherals which were in Azadi-I and few more this time, which were not stable at the time of Azadi-I. Azadi-II is also a final year project of undergrad students. The Azadi-II includes the following peripherals. I2C RISC-V Debug JTAG PWM 4-Channel with deadband enable OpenRAM 1KB x 4 for ICCM 1KB x 4 for DCCM Ibex core(named as brq_core) FPU (single-precision) TileLink (UL) UART PWM SPI GPIOs Design Goals: Azadi-II is aimed to extend the base ibex core(RV32IMC) with a fully functional single precision floating point unit and RISCV compliant debug module for on chip debugging and some standard peripherals for communicating with other devices. all these modules will be interlinked using standard Tilelink Bus protocol. Target Performance: for Azadi-II frequency is the main performance parameters. The target is to achieve 40MHz of sign-off frequency. In the previous version the frequency was about 50MHz.
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processor
sky130A