Brief Description:

This design utilizes recent machine learning modeling based on Linear delay lines incorporates linear temporal dynamics for neurally-based classifier approaches. The compiled SoC FPAA classifier required 20-30μW for a range of classification tasks [1,3-5]. We expect this new custom classifier component to require 20-40μW when the μP is turned off. The additional general linear dynamics block which allows for the detection of patterns over time. This block effectively allows each output category to have a preferred temporal signal instead of being classified based on a single spectral pattern.

This effort looks to compile this acoustic classifier network in a single Caraval Skywater platform utilizing and modifying the analog Floating-Gate (FG) standard cell library to place and route the final structure. The analog FG standard cell library, based upon experiences in FPAA devices, is currently in fabrication through Skywater 130nm CMOS.