Efabless Logo
ASIC Design of...
public project
MPW-4   

This project is the ASIC design of a 16-bit fault-tolerant ALU. As errors are very costly in mission-critical applications. The proposed ALU is implemented for space application by using the concept of hardware redundancy (TMR) with high fault-masking ratio (FMR) voter logic to tolerate the impacts of single event upset generated by radiation etc. and assure reliable functionality.

Fault Tolerant ALU using TMR

project layout image
project layout image
Layout Image
Owner
Uzair Ahmad
Organization URL

http://isb.nu.edu.pk/rfcs2/

Description

Space application Integrated Circuits (ICs) are prone to radiation particles, which are present in the form of electrons, protons, and heavy ions, generated from solar flares or space radiations. The circuits utilized in space applications must be able to tolerate these radiation impacts and assure reliable functionality. In this work, we have explored the impact of single-event upsets (SEUs) on the ALU architecture and proposed a fault-tolerant, 16-bit arithmetic logic unit (ALU) system, that works reliably in the presence of SEUs. The proposed architecture uses the concept of triple modular redundancy (TMR) with high fault-masking ratio (FMR) voter logic.

Version

V 1

Category

processor

Process

sky130A