The Block diagram have following blocks:
Proposed Design:
Description : Many efforts have been done to better utilize the fpga resources. Most of them are realtion to the routing resources of fpga. In the design proposed the bitstream loading cycle and execution is made parallel. Two memory blocks are added, in one memory block bitstream is being loaded, the other memory block (in which there is another bitstream loaded) is use to configure custom designed fpga.
eFpga is custom designed based on the mesh based architecture. State machine based control unit is designed, which will control the configuration block i.e it will configure the already loaded bitsream while also take the bitstream to upload in the other memory block.
For bitstream loading, an SPI is used to serially load the bitstream bit by bit.
Goal: Goal is to make the programmable SoC i.e ASIC of this cutsom designed efpga. As ASIC lack reocnfigurability. This ASIC of eFPGA will provide us with reconfigurability. while the same fpga can be used for larger application. Large application will be broken into many parts and there netlist will be converted to bitstream and this timemultiplexed parallel efpga can be used to implement it.
Target Performance: Target is to acheive 2X throughput increase while some compromise on area.
Why to make it: ASICs are costly and a have to bear a long flow in order to make post fabrication changes. In order to make an ASIC reconfigurable , custom design of efpga is proposed for ASIC so that programmable SoC. This will allow functionality to be changed after fabrication.
The propsed design will allow the pipelining in typical efppga hence increasing its throughput. Also a larger application can be implemented on same fpga by dividing into different bitstreams.
References:
Aken’Ova, V. O. (2005). Bridging the gap between soft and hard eFPGA design (T). University of British Columbia.
Team Members:
Custom design of eFpga with parallelism to improve throughput. During the bitstream loading cycle, the FPGA is kept idle and FPGA resources are wasted. In our design bitstream loading cycle and execution cycle are processed in parallel fashion. Implemented design is going to have two memory blocks. Large applications will be divided into multiple bitstreams and are loaded in time multiplexed fashion. This way while executing one bitstream, the other part of the program is being executed in an FPGA. This will increase the throughput while keeping the cost of FPGA relatively low