5G is playing a vital role in communication technology by enhancing communication system reliability, improving spectral efficiency, lowering the latency and power consumption of the system. As the demand for high data rate increasing exponentially [2], and the whole communication system shifted towards the massive multi-input multi-output (MMIMO) architecture is used in 5G technology to optimize beamforming and reduce interference, and fulfill the demand of the market. The problem arises in the analog front-end part of the system in the form of hardware complexity, cost, and area increase at an exponential rate and it is also power hungry [1]. Conversely, by replacing a high-resolution analog-to-digital converter (ADC) with a low-resolution ADC, complexity cost and power consumption of the whole system can be reduced. State of the art modeling work proves that substituting high-resolution (ADC) module of MMIMO can be replaced with low-resolution spatial ADC for same almost same SNR, resulting in lower power consumption and hardware costs [3]. Thus, channel estimation can be achieved by eliminating quantization error by using a low-resolution ADC/DAC. The quantization noise is shaped at higher frequencies by oversampling [4]. Out of band quantization noise can be eliminated by deploying the system in the spatial domain rather than temporal. Temporal domain also requires additional circuitry as shown in Figure. 1. Accordingly, propagation of quantization noise from one to another antenna is prior phase shifted at -∅ and then added to the input of adjacent antenna as shown in Figure. 2. Moreover, the channel estimation can also be achieved at the base station for MMIMO applications, where array of low resolution (1 to 2bit) ADCs are used through proposed model. Excess loop delay (ELD) Compensation scheme can be implemented that ensures modulator stability given a 1- clock-period ELD. This way we can enable the design of a 3rd-order single-bit modulator to clock at 6GHz in 45nm CMOS [5].
Figure 1. First-order one-bit Temporal Sigma-delta (∑Δ) Array
Figure 2. A first-order one-bit Spatial Sigma-delta (∑∆) array with shifting of Quantization noise from one antenna to the adjacent antenna by shifting at -∅
In this work, we proposed the complete module of spatial ∑Δ ADC consisting of modulator and digital low-pass filter (LPF). The digital output will be fed to the RISC-V Core. The proposed design is targeted for the 5G applications. The proposed hardware implementation of spatial ∑Δ ADC for MMIMO utilizes a single-bit DAC, which yields high linearity. The proposed design consists of 4th order oversampling ∑Δ modulator. The proposed modulator block of the proposed ∑Δ ADC will be implemented on open source analog design tool, while the digital filter is modeled in MATLAB, and on chip implementation will be realized by open source digital design process flow in the SKY130 CMOS process.
In MMIMO architecture, all the outputs of the ADCs are summed up. By adding all the outputs of the ADCs, all the quantization noise will be cancelled out, and only the last stage noise will remain in the system, which is acceptable. The block diagram of the proposed system with symbolic waveform for practically implementable non-ideal components and non-zero delay is shown in Figure 3. The quantization noise of previous stage is added into the output of the next antenna, and the process through ADC. Positive and negative spikes are cancelled by adding up. If ideal quantizer is assumed, then all the noise will cancel out. The same process repeats for “n” antennas. In proposed architecture, signal from the all antennas are added up, while quantization noise of only last stage appears at output of overall MMIMO system. However, due to delay mismatch and components non-ideality noise is not eliminated entirely. Digitally modulated signal (Y) is finally passed through digital low pass filter (LPF), which provides high SNDR. The target specifications of the proposed ∑Δ ADC are summarized in Table 1.
Figure 3. Block diagram of proposed architecture of spatial sigma-delta ADC and signal waveform for non-ideal components and non-zero delay in the system, all the quantization noise will not cancel out at a second and third stage.
Specifications |
Target |
Bandwidth |
2 MHz |
Order |
4 |
Signal to Noise and Distortion Ratio (SNDR) |
> 55 dB |
Over Sampling Ratio (OSR) |
40 |
Active Area |
< 1 mm^{2} |
[1] M. Shao, W. K. Ma, Q. Li, and L. Swindlehurst, “Spatial Sigma-Delta Modulation for the Massive MIMO Downlink,” 53rd Asilomar Conference on Signals, Systems, and Computers, pp. 833–837, 2019.
[2] P. Jonsson et al., “Ericsson Mobility Report. November 2017,” pp. 31, 2017.
[3] G. Manganaro, “A Wideband Analog Front End Based on a Continuous Time, ∆-Σ High Speed ADC Reduces Power Consumption of High Performance Communication and Instrumentation Systems | Analog Devices,” pp. 1–2, 2015.
[4] S. Rao, G. Seco-Granados, H. Pirzadeh, J. A. Nossek, and A. L. Swindlehurst, “Massive MIMO Channel Estimation With Low-Resolution Spatial Sigma-Delta ADCs,” IEEE Access, vol. 9, pp. 109320–109334, 2021.
[5] V. Srinivasan, V. Wang, P. Satarzadeh, B. Haroun, and M. Corsi, “A 20mW 61dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS,” IEEE International Solid-State Circuits Conference, pp. 158-160, Feb. 01, 2012.
Engr. Muhammad Dawood Asghar (i212431@nu.edu.pk)
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In this proposal we have proposed Spatial Sigma-Delta ADC for MMIMO 5G applications with a bandwidth requirement of 2 MHz. The proposed design operates at oversampling ratio of 40, and provides SNDR of more than 55dB. The implementation on 130 nm process utilizes an active area of less than 1mm2. The proposed design is inspired from mathematical modeling presented in MMIMO channel estimation using low resolution ∑Δ ADCs, published in IEEE Access [1].
Final Version
adc