Abstract:  

Data encryption is necessary in military as well as in other security concerned applications. Pseudo Random Number Generator (PRNG) is used to encrypt data to generate unpredictable and Indeterministic sequence of numbers at higher frequency. Linear Feedback Shift Register (LFSR) are widely used to design PRNG with the seed implemented to the D-Flip Flop. A PRNG with 4-bit LFSR is proposed in this project, with 32 number of LFSRs that will be able to generate the random data of 4 x 32 bit. The circuit of the proposed work will be implemented with Gate diffusion Input (GDI) and standard CMOS techniques opted for SKY 130 PDK. GDI and CMOS techniques reduces the required active area and power consumption.  

Motivation 

Due to COVID-19 pandemic, most of the tasks have shifted to an online platform. Sectors such as E-commerce, sensitive multi-media transfer, online banking have skyrocketed [1]. Because of this, there is a huge demand of secure algorithms, which cannot be hacked into by unauthorized users. The method which is the backbone for building encryption algorithms is the Random Number Generation (RNG). Random number must be generated based on chaotic maps, that are mathematical functions that generate a highly arbitrary pattern based on the seed value [2]. The seed values must have minimum correlation and maximum entropy to make the system most chaotic and unpredictable. Many digital algorithms have been designed to provide data encryption, but the need today is the design of hardware resources that must be equivalent capable of generating the sequence designed at lower silicon cost and lower power consumption. The architecture design using Gate Diffusion Input (GDI) and Hybrid CMOS logic gates provides an optimal solution to the low power and area utilization needs [3]. The GDI structure is suitable for the design of fast and low-power circuits using a reduced number of transistors, while improving logic level swing, static power characteristics and allowing simple top-down design by using small cell library [4].  

Proposed Circuit 

In this work, we propose a Pseudo Random Number Generator (PRNG) using Linear Feedback Shift Register (LFSR) with having the seed input at the D-Flip Flop [5]. The Fig. 1 shows the overall block diagram of the proposed system that is designed to have minimum area and lower power consumption to make it implementable inside chip and in nano-scale technology. The seed value is inserted to the flip flop that further feeds the LFSR to generate the random sequence. To make the PRNG reliable for larger number of combinations and for higher frequency the randomness in the structure must be increased.  Chaotic algorithms will be used on the to generate numbers with high level of randomness. The LFSR is proposed to design using d flip flops using hybrid CMOS and GDI technique to minimize the transistor count and power [6].  

Figure 1: Proposed Block Diagram for PRNG using LFSR  

Fig 1 shows the cascading of the D flip flop to design the LFSR that will further be used to generate random numbers. PRNG becomes deterministic and starts repeating its cycle if the system remains linear for some good amount of time. One technique for destroying the linearity inherent in LFSRs is to use several LFSRs in parallel [7].  The structure of the nonlinear combining generator with good statistical properties and long periods is as shown in the LFSR block of the block diagram. The LFSRs are combined with a nonlinear logical function so that the nonlinear combining generator can be robust against the cryptographic attack. This function is known as the merge function. The simplest f function is XOR, which will be designed here using the GDI structure to further optimize the area and power. The choice of the LFSR structure and function f is important to generate random numbers with the nonlinear combining generator. In our design we will implement the structure as described in paper [7] but the building blocks will be designed using hybrid CMOS and GDI structures. 

Proposed Target

The system is designed to achieve the following target parameters.

Table 1 Specification Target for the DFF

References 

[1] Naik, R. B., & Singh, U. (2022). A Review on Applications of Chaotic Maps in Pseudo-Random Number Generators and Encryption. Annals of Data Science, 1-26.

[2] Paul, P. S., Sadia, M., Hossain, M. R., Muldrey, B., & Hasan, M. S. (2022). Cascading CMOS- Based Chaotic Maps for Improved Performance and its Application in Efficient RNG Design. IEEE Access.

[3] Foroutan, V., Taheri, M., Navi, K., & Mazreah, A. A. (2014). Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style. Integration, 47(1), 48-61.

[4] Morgenshtein, A., Fish, A., & Wagner, I. A. (2002). Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits. IEEE transactions on very large scale integration (VLSI) systems, 10(5), 566581.

[5] Yang, W. H., Chu, L. C., Yang, S. H., Lai, Y. J., Chen, S. Q., Chen, K. H., ... & Tsai, T. Y. (2018, February). An enhanced-security buck DC-DC converter with true-random-number-based pseudo hysteresis controller for Internet-of-Everything (IoE) devices. In 2018 IEEE International Solid-State Circuits Conference(ISSCC) (pp. 126-128). IEEE.

[6] Sharma, R., & Singh, B. (2016, October). Design and analysis of linear feedback shift register (LFSR) using gate diffusion input (GDI) technique. In 2016 5th International Conference on Wireless Networks and Embedded Systems (WECON) (pp. 1-5). IEEE.

[7] Tuncer, T., & Avaroğlu, E. (2017, May). Random number generation with LFSR based stream cipher algorithms. In 2017 40th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO) (pp. 171-175). IEEE.

Team lead:    

Engr. Sonia Kiran (i212444@nu.edu.pk)  NUCES (FAST-NU)

Team members:                       

Engr. Ali Sabir  NUCES (FAST-NU)

Engr. Mudassir Ali  NUCES (FAST-NU)

Engr. Faizan Khan   NUCES (FAST-NU)

Engr. Farid-ud-din  NUCES (FAST-NU)

Dr. Hassan Saif  NUCES (FAST-NU)

Dr. Rashad Ramzan  NUCES (FAST-NU)