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Subthreshold SRAM
public project

Low Power Subthreshold SRAM for biomedical Applications


Memories in biomedical systems needs to be highly power efficient to prolong battery life. Whereas, their performance constraints are considerably relaxed. Biomedical wearable systems such as body-area sensors and hearing aids, battery lifetime determines the time between battery replacements. This constraint requires that power consumption of less than 100uW. Since, the minimum energy point lies in subthreshold region [1], so that is the main driving force to operate the memories in subthreshold region. Figure 1 depicts the SRAM architecture, which consists of following blocks:

  1. Memory Array (Consists of Low power cell)
  2. Row & Block Decoder
  3. Column Multiplexer
  4. Pre-charge Circuit (For bit-line charging)
  5. Sense Amplifiers
  6. I/O Flip flops
  7. Controller Unit (For generation of Read/Write signals)

Fig.1:  SRAM architecture that includes memory array, decoder, pre-charge circuit, sense amplifier, column multiplexer and control unit.

Fig.1:  SRAM architecture that includes memory array, decoder, pre-charge circuit, sense amplifier, column multiplexer and control unit.

Proposed SRAM Cell:

SRAM mainly consists of back-to-back inverters for data storage. The primary challenge of writing into the memory is to overcome this positive feedback from back-to-back inverters. The proposed design, uses stack PMOS transistors, is data aware means that before writing into the memory it blocks the voltage (so that there would be no fight between already present data and the incoming data). In this way, both write energy and timings are improved in the proposed design. The schematic of the proposed subthreshold SRAM cell is shown in Figure 2. This design is inspired from this VLSI paper [2].

 Fig. 2: Schematic of the proposed low power Subthreshold SRAM bitcell


This design has several features. Firstly, It is data aware and it uses single bitline for writing operation, when the data is ‘1’, it turned on M8 and turned off M6 and similarly when data is ‘0’, it turned on M7 and turned off M5 in order to avoid the fight between already present data and incoming data. In [2], it uses write assist techniques such as word line boosting and negative bit line, which not only increase the silicon area (by generating those voltages on chip) but also make the circuit operation complex. In the proposed design, there is no write assist is used at all. Secondly, the energy and performance figures are better in the proposed design as compared to [2] . Thirdly, the proposed design uses dynamic voltage scaling (DVS) in order to achieve low power. Finally, the data retention voltage (DRV) is estimated by using Monte Carlo simulations and cell is sized for Read static noise margin (SNM) of 100mV. The target specifications of the proposed design are summarized in Table 1.


                               Table 1 Target Specifications



Memory Size


Frequency @ 2.4V and @0.4V

 2.2GHz and 76MHz

Energy/bit @ 2.4V and @0.4V

825fJ and 8.65 fJ

Leakage Power @0.4V


Hold/Read SNM


Team Lead: Engr. Abdul Wajjid (i191321@nu.edu.pk)

Team Members:

  • Hamza Atiq
  • Hassan Saif
  • Dr. Rashad Ramzan



N. Verma and A. Chandrakasan, “A 65 nm 8T sub-V SRAM employing sense-amplifier redundancy,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2007, pp. 328–329.


C. -Y. Lu et al., “A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist,’’ in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 5, pp. 958-962, May 2015.




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This is a proposal for IEEE PICO design contest 2022. A low power subthreshold SRAM cell is proposed here for biomedical application. The proposed design of 1kbit memory offers moderate performance of 2.2GHz, low leakage power in standby mode (<100nW), and substantial hold static noise margin (>100mV) that meets biomedical application requirements. The design is an improvement on a low power SRAM design published in IEEE Transactions on VLSI.