<A 6-Gb/s 3-tap FFE Transmitter for Wireline Communication Systems>

Description

In this project, we design a transmitter with a feed-forward equalization capability to compensate Inter-Symbol Interference (ISI) from band-limited channels. The transmitter adopts the current-mode driver structure for high-speed operation, with additional taps to implement a feed-forward equalization function.

If there is data to transmit, it is received in parallel. TX_DATA received in parallel passes through Data Reiciver. The clock used here must have a high operating frequency for fast data. A clock is generated by using a PLL having an accurate and fast frequency and low jitter. Serialized data are transmitted through driver. The data is passed through sign decision and then through Pre-Driver and Main-Driver, and the Main-Driver accepts inputs from three paths. We use Pre-Driver because it is burdensome to drive Main-Driver all at once.

Design goals

The transmitter frontend we are planning to implement is targeting for achieving >6Gb/s data-rate, to be compatible to many of industry standards, such as DisplayPort 1.2 (5.4Gb/s) and USB 3.0 (5Gb/s). The design is expected to provide a 3-tap feed-forward equalization (FFE) capability as well, to compensate distortions from channel loss. Current mode tap cells are used for implementing the FFE function with minimal capacitive loadings, to achieve the high data-rate in a 130nm CMOS technology. The current consumption is expected to be less than 40mA.

Block Diagram

Schematics

Pre-Driver

Driver

Target Specification

References

[1] A. Roshan-Zamir, O. Elhadidy, H. Yang and S. Palermo, "A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 52, no. 9, pp. 2430-2447, Sep. 2017.

[2] J. Lee, M. Chen and H. Wang, “Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data,” in IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 2120-2133, Sep. 2008.

[3] F. Celik, A. Akkaya, A. Tajalli, and Y. Leblebici, “A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI,” in IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 6, pp. 1132-1140, Jun. 2021.

[4] H. Chen, D. Wang, Z. Wang, S. Yuan, C. Zhang and Z. Wang, "An 11.05 mW/Gbps Quad-Channel 1.25-10.3125 Gbps Serial Transceiver With a 2-Tap Adaptive DFE and a 3-Tap Transmit FFE in 40 nm CMOS," in IEEE Access, vol. 9, pp. 70856-70867, 2021.

[5] J. F. Bulzacchelli et al., "A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology," in IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2885-2900, Dec. 2006.

Team Members:

1. JaeDuck Han: Team Advisor
   • Professor, Dept of Electronic Engineering(EE), University of Hanyang
2. ChangJo Choi: Team Leader
   • Undergraduate Student, Dept of EE, University of Hanyang
3. DongSeon Kim: Member
   • Undergraduate Student, Dept of EE, University of Hanyang
4. HyungJoo Park: Member
   • Undergraduate Student, Dept of EE, University of Hanyang