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Caravel Plus
public project
MPW-1

Caravel Plus

Caravel management SoC attached to the largest possible DFFRAM that can fit the user's area. For the RAM related development, refer to DFFRAM

Caravel Integration

Verilog View

The DFFRAM macro is placed on the management area wishbone bus at address (0x30000000). For the memory interface and wishbone bus conversion, refer to Caravel_RAM_24KB_wb

GDS View

If you are collaborating on this project, please click here to access your collaboration files, and click "Accept Share" in the actions column if you haven't done so already.

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Organization URL

http://efabless.com

Summary

Caravel management SoC attached to the largest possible SRAM that can fit the user's area.

Version

1.00

Process

sky130A