A phase-locked loop is a feedback system combining a voltage controlled oscillator (VCO) and a phase comparator so connected that the oscillator maintains a constant phase angle relative to a reference signal. The main objective of a PLL is to generate a signal in which the phase is the same as the phase of a reference signal.[1]
The basic blocks of the PLL are the Error Detector (composed of a phase frequency detector and a charge pump), Loop Filter, VCO, and a Feedback Divider. Negative feedback forces the error signal, e(s), to approach zero at which point the feedback divider output and the reference frequency are in phase and frequency lock, and FO = NFREF.[1]
A system for using a PLL to generate higher frequencies than the input, the VCO oscillates at an angular frequency of ωO. A portion of this signal is fed back to the error detector, via a frequency divider with a ratio 1/N. This divided down frequency is fed to one input of the error detector. The other input in this example is a fixed reference signal. The error detector compares the signals at both inputs. When the two signal inputs are equal in phase and
frequency, the error will be constant and the loop is said to be in a “locked” condition.[1]
Block Diagram of Phase Lock Loop [2]
PLL consists of five major blocks:
Phase Frequency Detector:
The “Phase frequency Detector” (PFD) is one of the main part in PLL circuits. It compares the phase and frequency difference between the reference clock and the feedback clock. Depending upon the phase and frequency deviation, it generates two output signals “UP” and “DOWN”.[2]
Charge Pump:
Charge pump circuit is used to combine both the outputs of the PFD and give a single output which is fed to the input of the filter.The amplitude of the current always remains same but the polarity changes which depend on the value of the “UP” and “DOWN” signal.[2]
Loop Filter:
The passive low pass loop filter is used to convert back the charge pump current into the voltage. It cancels high frequencies and keeps DC component of erro rsignal .The output voltage of the loop filter controls the oscillation frequency of the VCO.[2]
Voltage Controlled Oscillator:
Voltage controlled Oscillator provides local frequency for the circuit. It is controlled by the error signal from phase detector.[3]
Frequency Divider:
Frequency Divider is used to reduce the frequency that is obtained from VCO The frequency divider in the PLL circuit forms a closed loop. It is the one which converts the oscillator high output frequency to a lower frequency which can be compared to a reference source.[2]
Phase Detector [4]
Charge Pump [5]
Loop FIlter [5]
VCO [5]
Frequncy Divider [5]
| VDD | 1.8 V |
| Input frequency | 10 MHz |
| Output frequency | 100 Mhz |
| Total current consumption | 5 mA (max) |
| Output Jitter | TBD |
[1] MT-08 Tutorial- Fundamentals of Phase Locked Loops -Analog devices
[2] Gande Bhargav,Govind Prasad, Srikar Datta Canchi,Badam Chanikya-"Design and analysis of phase locked loop in 90nm CMOS." 2016 Thirteenth International Conference on Wireless and Optical Communications Networks (WOCN)
[3] Tutorial overview of Analog PLL's - ECG21 - Shada Sharif
[4] Naheem Adesina, Ashok Srivastava - "Memristor-based loop filter design for phased locked loop." J. Low power Electron .Appl. 2019
[5] Intissar Toihria, Rim Ayadi, Mohamed Masmoudi - "Design of an Effective Charge Pump-Phase Locked Loops Architecture for RF Applications." International Journal of Computer Applications (0975 – 8887)
Pranav D Lulu , B.Tech Student , Dept of E&TC , VIIT Pune
Omkar R Magar , B.Tech Student , Dept of E&TC , VIIT Pune
Vedant S Phapale , B.Tech Student , Dept of E&TC , VIIT Pune
This design contains a Phase Locked Loop which can be used in high frequency applications. The design of PLL will be done using Skywater 130 PDK and open source IC design tools.
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