Design:
5 stage RISC-V pipelined process supporting assembly language. Implementation of basic intsruction set of risc v like load, store, add, beq etc. Any assembly code can be run on this pipelined processor. Pipelining make the processor faster than the single stage processor. In single stage RISC V processor an nect instruction waits until the first instruction is executed. but in pipelining many instructions can run in parallel. following are the stages of pipelined processor:
FOrwarding unit is implemented for the instructions which uses the data of just evaluated instruction i.e the output if execution stage . for this forwarding unit is use which forwards the evaluated iutout immediately to intermediate state rather than waiting for it to go to memory and then read from there.
Hazard detection unit is essential for the instructions like jump , for intsnace ALU evalutes that two registers become equal and there is a condition of jump if they equal then hazard detection unit detects it and reset the control signals, flush the instructions that are parallely processing in the pipeline.
Team Members:
Implementation of RISC V processor with 5 stage pipelining Addition of Bypass interlock and stalling circuitry . Testing of basic instructions such as add, load, store, beq. Any assembly code can then be run on this processor.
processor