In this project we are going to perform implementation of two different topologies of random-access memories including 6T SRAM (six transistor) and 1T DRAM (one transistor).
1T DRAM should require smaller area given it require lesser number of transistors where as SRAM is suppose to be faster and power efficient.
Structure of 6T stores one bit information along with its complimentary data on two bitlines located at either side of the cell. The core of the memory cell is formed using CMOS inverters having output potential of each inverter fed as input into the other making a feedback loop, stabilizing inverters to their respective state. Access transistors having input WL at their gate are used to access the cell along with BL and BLbar to read and write to the cell. In standby mode the word line is low, turning the access transistors off having inverters in complementary state.
To write information over bitlines, inverse data on BL and BLbar is imposed while turning on word line keeping access transistors high. As soon as the information is stored, the access transistors can be turned off and the information in inverters is preserved. To read this data, the word line is turned on to and the information is sensed at the bitlines.
On broader scale, the entire system consists of following functionalities and modules.
This is the basic SRAM cell storing one bit of data. We are going to repeat this multiple times (n times ) in either direction to store eight different nxn-bit data.
Pre-charge is used to charge the bitline to a certain value (either vdd or vdd/2) so that we can read the data based on difference in voltage in the cell and bitline. Precharge at vdd/2 makes it further sure that we don’t write accidently on bitline while reading from the cell.
This comprises of PMOS transistors with gates connected together so that the output can be controlled using a single precharge enable signal
We used a NOR logic-based decoder. This decoder is used to control the bit lines using 3 inputs which further drive 8-word lines of 8 different rows of cell. The output of this decoder is adjusted as per the read and write strobes and in which row we want to write the given data.
We are using sense amplifiers at the end of bitlines to read the contents of several memory since they achieve a fast decision due to strong positive feedback. A small difference between the currents of sense amplifier input provided by complementary bitlines converts to a large output voltage
Design modules for our version of 1T DRAM are quite similar except for the cell itself. The main difference is additional circuitry is that we don’t need an additional complementary bitline (Bitlinebar) signal to be accommodated for precharge, read, and write circuit.
We are going to compare the results for current and power drawn, area covered. We are also going to measure read and write access times for both type of RAM
A memory accessing system may perform better depending upon the type of random-access memory configuration it is using. The requirements for memory access may include fast memory access, power efficiency, or amount of data it can hold. In this project we are going to perform implementation of two different topologies of random-access memories including 6T SRAM (six transistor) and 1T DRAM (one transistor) and compare their performance for different constraints and requirements of applications. The area occupied by the 1T DRAM should be less than that of 6T SRAM because of relatively lesser number of transistors. Static RAM will suppose to be faster and relatively power efficient as compare of DRAM. These requirements of application include area, read write access time, and power requirements. The entire system consists of memory core array(6T and 1T), precharge circuitry, write circuitry, decoders circuit, inverters, sense amplifiers and read circuitry.
sram