An Application Specific Integrated Circuit, as the name suggests, performs a specific task. In this project, an ASIC is designed for a smart garden. Whole work flow can be divided into 3 parts:
1. Collecting data from the sensors.
2. Processing data.
3. Output based on the data.

4. Transmission of data every 5 minute.

Architecture: ASIC in this project is divided into Analog, Digital and Mixed signal part. Mixed Signal part contains ADC which is used to convert the analog data collected by sensors (such as temperature, humidity, rain, moisture) to bits. Finite State Machine(FSM) from digital Part then makes decision based on its value. The Digital Part will then store data to the integrated 128x32 RAM every minute by the use of integrated Timer. FSM output is connected to Decoder and the output of Decoder will be the Digital Output of the ASIC which can then be connected to relays and valves for garden application. ASIC will have RF transmitter to send collected data every 5 minutes. RF transmitter will be composed of UART, Amplitude Shift Key (ASK) and Power Amplifier. It will operate in 900 MHz under ISM band. Finite State Machine (FSM) is used instead of a general-purpose CPU as FSM is highly efficient in terms of computation and power with the cost of flexibility and programmability. Apart from that, digital signal to analog and fed to Amplitude Shift Key (ASK).

Design is performed using open-source tools such as eSim integrated with ngveri and makerchip. Will be using Skywater pdk technology to implement the design.

Upgradation: We plan to add different communication interface such as I2C, SPI. Also, PLL block will be added for ASK input. BGR block will be added for maintaining a constant supply. Apart from that, Power amplifier and GPIO.

Project Significance: This project contains ADC/DAC block which can contribute to the wanted open-source IP, 12bit ADC/DAC.
Apart from that. It uses several existing open-source IP.

Block Diagram: (An abstract view)

Schematic of Different Parts:     

Target Performance Summary:

Reference:
[1] M. Karimi-Ghartemani and M.R. Iravani, “A New Phase-Locked Loop (PLL) System” Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)

[2] Pengfei Zhang, “Design of CMOS LC Oscillators” 2006 8th International Conference on Solid-State and Integrated Circuit Technology

[3] Hironori Banba, Hitoshi Shiga, Akira Umezawa, Takeshi Miyaba, Toru Tanzawa, Shigeru Atsumi, and Koji Sakui, “A CMOS Bandgap Reference Circuit with Sub-1-V Operation” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 5, MAY 1999

[4] Mohammed A. A. Elmaleeh, N. Saad, Joe Pahor, Bandar Seri Iskandar, “A Modified Version of 12-Bit Tracking Analog to Digital Converter for High-Stability Output Tracking” International Conference on Intelligent and Advanced Systems 2007

[5] Proceedings Sayed-Am El-Hamamsy, “Design of High-Efficiency RF Class-D Power Amplifier” IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 9, NO. 3, MAY 1994.

[6] Guan-Chyun Hsieh, James C. Hung, “Phase-Locked Loop Techniques-A Survey” IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 43, NO. 6, DECEMBER 1996.

[7]Umakanta Nanda, Sushant Kumar Pattnaik, “Universal Asynchronous Receiver and Transmitter (UART)” 2016 3rd International Conference on Advanced Computing and Communication Systems (ICACCS -2016), Jan. 22 – 23, 2016, Coimbatore, INDIA.

[8] Ye Jianfei,Li Zhaolin, Wei Chipin, Zheng Qingwei, Chen Jiajia, “Design of a Configurable General-Purpose Input/Output with Event-Capture” 2010 Second Pacific-Asia Conference on Circuits, Communications and System (PACCS).

Team Members:
1. Glen Frey Olamit, from Philippines
2. Antun Babundin, from Russia
3. Kishan Singhania, from India
4. Mohammad Redwan Islam, from Bangladesh