A Phase Locked Loop (PLL) has many applications such as frequency synthesis, clock-data recovery and filtering the jitter of a reference clock. PLLs are typically found in systems requiring clocks such as Microprocessors, Wireline and Wireless Communication, and Data Converters. Though charge-pump based analog PLLs meet the performance requirements, the loop filter occupies a large area and does not benefit from CMOS scaling due to artifacts such as increased current mismatch and leakage. The goal of this project is to design a digitally enhanced PLL that implements the loop filter in the digital domain. The digital PLL results in compact realization of the loop filter that is immune to PVT variations and can benefit from CMOS scaling.  

Working Principle:

The block diagram of a digital PLL is shown in Fig 1. Like the analog PLL, it consists of a tunable frequency generator called a voltage controlled oscillator (VCO). A frequency divider in the feedback path divides the VCO output clock (HS_CLK) by a factor of N to generate the feedback clock (FB_CLK) [1]. The phase detector and charge pump of the analog PLL are replaced by a time to digital converter (TDC) and a digital loop filter [2][3]. The TDC digitizes the  phase difference between the FB_CLK and the incoming reference clock (REF_CLK).  This phase error is integrated by the digital loop filter. A digital to analog converter (DAC) converts the output code of the digital loop filter to adjust the control voltage (Vc). This negative feedback action locks the phase and frequency of the FB_CLK to the REF_CLK. In the locked condition, the frequency of the FB_CLK is the same as the frequency of the REF_CLK. Since FB_CLK is generated by dividing the HS_CLK by N, the output clock of the VCO (hence the PLL) has a frequency of N*REF_CLK.

Fig 1. Block Diagram of a Digital PLL

Implementation:

The goal of this project is to design a PLL that receives an input reference clock in the range of 20-50MHz and synthesizes a high frequency clock in the range of 320-800 MHz. The feedback divider divides HS_CLK by 16 to generate FB_CLK. A current starved ring oscillator based VCO [4] allows for wide output frequency range of the PLL. The PLL operates on a single 1.8 V supply. The schematic of TDC based on Phase Frequency Detector (PFD) and bang-bang phase detector (!!PD) is shown in Figure 3 [5]. The digital loop filter is a first order accumulator. The 14b output of the digital loop filter is noise-shaped and re-quantized to 4b using a delta-sigma modulator. The 4b DAC is implemented by turning on/off current sources into a resistor, as shown in Fig 4. Not shown in Fig 4. is a constant I independent of DAC code that ensures a minimum Vc. 

Fig 2. Current Starved VCO based Ring Oscillator and Feedback Divider 

Fig 3. TDC, Loop Filter and DAC

Fig 4. DAC Implementation

It is helpful to add force and probe points in the design so that each block in the design can be independently validated post-silicon. The DAC can be tested by forcing the DAC code and observing the control voltage. The VCO can be tested by forcing the DAC code and observing the divided version of the VCO clock (on low speed IO). The TDC operation can be tested by independently forcing it’s inputs and observing the UP/DN signals and !!PD output.  

Specifications:

Members:

The analog club at University of Texas at Austin is proposing the design of a Digital Phase Locked Loop (PLL) in order to help members explore the process of IC design in a setting unique to undergraduate students. Assisted by graduate mentors, our team of undergraduate students is excited to start working and learning on this chipathon in order to gain exposure to IC Design while contributing to the open source community. We would like to thank Prof. Mark McDermott and Prof. Yaoyao Jia for their guidance in preparing the project proposal.

Undergraduate Students:

1. Spencer B. Denton, Second Year BS in ECE
2. Andrew Bacon, Third Year BS in ECE
3. Parth Shroff, Second Year BS in ECE; Second Year BS in Computer Science Honors
4. Manthan Upadhyaya, Third Year BS in ECE
5. Isha Chakraborty, Third Year BS in ECE
6. Humza Syed, Third Year BS in ECE
7. Victoria Tyler, Second Year BS in ECE
8. Raymond Jiang, First year BS in ECE
9. Jordan Doan, Third Year BS in ECE

Graduate Students:

1. Vic Frederick, second year MS in ECE
2. Sumanth Karanth, First Year MS in ECE
3. Sirish Oruganti, First Year PhD in ECE
4. Jacob N Rohan, Fourth Year PhD in ECE
5. Vinay B Vishnani, First year MS in ECE
6. Pooja Narsingdas Kakani, First year MS in ECE 
7. Atharva Karaguppi, First year MS in ECE
8. Srinivas Bangalore Seshadri, First Year MS in ECE

References:

1. Dennis Fischette, IEEE SSCS Distinguished Lecturer Series PLL Tutorial, https://www.delroy.com/PLL_dir/pll.htm
2.  K. Hanumolu, G. Wei, U. Moon and K. Mayaram, "Digitally-Enhanced Phase-Locking Circuits," 2007 IEEE Custom Integrated Circuits Conference, 2007, pp. 361-368, doi: 10.1109/CICC.2007.4405753.
3. K. Hanumolu, M. G. Kim, G. Wei and U. Moon, "A 1.6Gbps Digital Clock and Data Recovery Circuit," IEEE Custom Integrated Circuits Conference 2006, 2006, pp. 603-606, doi: 10.1109/CICC.2006.320829.
4. D. K. Jeong, G. Borriello, D. A. Hodges and R. H. Katz, "Design of PLL-based clock generation circuits," in IEEE Journal of Solid-State Circuits, vol. 22, no. 2, pp. 255-261, April 1987, doi: 10.1109/JSSC.1987.1052710.
5. Yin, R. Inti, A. Elshazly, B. Young and P. K. Hanumolu, "A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking," in IEEE Journal of Solid-State Circuits, vol. 46, no. 8, pp. 1870-1880, Aug. 2011, doi: 10.1109/JSSC.2011.2157259.
6. Kyle Pierce, David Kotecki, "Phase-Lock Loop (PLL) and Testing with LabVIEW," University of Maine, 2001.https://ece.umaine.edu/wp-content/uploads/sites/203/2012/06/pll_test_report.pdf