SRAM Example

Overview

The SRAM example utilizes Caravel and commercial SRAM provided by Efabless. This example shows how to integrate the SRAM macro in the user project space, and use a Wishbone Bus controller to communicate with the RiscV processor.

User Project Features:

• 1024x32 Commercial SRAM
• Wishbone Bus controller

SRAM Features

• Synchronous Read-Write
• Active High Bit Enables
• Single Read-Write Enable (Low = write, High = read)
• Write on a bit basis
• Separate pins for data input and data output
• Separate Power Supplies for core and periphery
• Body bias option
• Scan Chain Testmode
• Wafer Level Burn-In Testmode
• Option to switch off all wordlines while chip is enabled
• Option for Power Switch
• Clock Gating

Block Diagram

Getting Started

For more information and setup/implementation documentation visit SRAM integration knowledgebase document

For more information about the SRAM macro visit SRAM catalog entry