The designing Discrete-Time Delta-Sigma Modulator (DC DSM) as a project will be appropriate for a new designer with analog and mixed-signal specialization, and an especially interest in analog-to-digital converters. In this project, the junior designer will do a study on DSM to discover
trade-offs the design and optimize the design to obtain high-resolution conversion in embedded applications.
The main objective of this project is to define a state-of-the-art high-resolution DSM with the main feature such as approximate 10 bits resolution, 5MHz bandwidth, and above 256MHz conversion rate. Oversampling ratio (OSR) is approximately 25. A behavioral model was developed in the feasibility study to derive a complete design specification for a third-order fully differential discrete DSM.
Due to specification is already chosen at that project, there are four main aspects of the architecture where one can modify it: time domain, order of loop filter, topology, and the number of bits of the quantizer to obtain the desired result. In this chapter, we will review the different alternatives for architecture with respect to the four aspects. To ease the discussion, we will mainly focus on discrete-time cascaded integrator topologies. Oversampling ratio is also known. Therefore, there are only two parameters that should be chosen.
In the figure below[1], it is shown how much OSR one needs to achieve an ideal SQNR, for a different order of integrator (L represents the order of the integrator). It can be observed to achieve 10-bit resolution, modulators on the order of 2 and 3 are sufficient. It can also be observed that the modulator with order 2 needs a much larger OSR, which can cause problems with (sampling frequency)/ (Nyquist frequency), and we are already stacked at the number of the OSR, therefore, the 3rd order is chosen for this project
Instability is an issue higher-order filters are struggling with. For first-order and second-order filters, this is not a problem, but as the order of the filters gets bigger, the out-of-band gain (OBG) of the modulator gets more aggressive. The high OBG can cause overloading of the quantizer which can make the modulator unstable. Moreover, the third-order with one-bit feedback can be insufficient for 12-bit resolution. Therefore, 4-bit feedback will be used at the project to ensure specs. This 4-bit feedback is planned to design by a combination of the 4-bit Flash ADC using Strong-Arm Latch as a comparator [2] [3] and R string DAC.
When all parameters are defined, these parameters are tested at Delta-Sigma Toolbox at MATLAB [4]. The simulation result of it shown below. The obtained SQNR is sufficient to design DSM. It gives us about 12.12 bits.
When the theoretical parts are corrected, the design process is begun. The CRFB (Cascaded resonator feedback) is chosen as architecture because it is the very common structure in the DSM design and is easy to implement. The block diagram of the design is shown in the next chapter [1]. The parameter of this structure is obtained from the DSM Toolbox.
The structure is Discrete Time, so the integrators are also discrete-time [5]. The DSM is containing mainly two integrators: delaying and non-delaying. The schematic of the integrators used is shown Schematics section. There is only a difference some switches have different phases shown in the figure. The first and third-order use delaying integrator, the other use non-delaying configuration. The fully differential version of them is planned to use at the project.
[1]R. Schreier and G. C. Temes, ”Understanding Delta-Sigma Data Converters”, New York, IEEE press, Wiley-Interscience, ISBN:0-471-46585-2, 2005
[2] B. Razavi, "The Design of a Comparator [The Analog Mind]," IEEE Solid-State Circuits Magazine, Volume. 12, Issue. 4, pp. 8-14, Fall 2020.
[3] B. Razavi, "The Flash ADC [A Circuit for All Seasons]," IEEE Solid-State Circuits Magazine, Volume. 9, Issue. 3, pp. 9-13, Summer 2017.
[4] Schreier, Richard & Pavan, Shanthi. (2017). The Delta‐Sigma Toolbox. 10.1002/9781119258308.app2.
[5] B. Razavi, "The Switched-Capacitor Integrator [A Circuit for All Seasons]," IEEE Solid-State Circuits Magazine, Volume. 9, Issue. 1, pp. 9-11, Winter 2017.
[6] B. Razavi, "The Delta-Sigma Modulator [A Circuit for All Seasons]," IEEE Solid-State Circuits Magazine, Volume. 8, Issue. 20, pp. 10-15, Spring 2016.
As a project, I pick the Discrete Delta-Sigma Modulator (DC DSM). The main objective is to define a state-of-the-art high-resolution DC DSM with the main features such as approximate 10 bits resolution, 5 MHz bandwidth, and above 256 MHz conversion rate (oversampling ratio (OSR) apx. 25).
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